[ARM64] EXT and EXTR instructions on v8i8 and W regs respectively must have the top...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205881 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM64/ARM64InstrFormats.td b/lib/Target/ARM64/ARM64InstrFormats.td
index f1981bf7499aa9460a81f2328a516eda8cca6285..aeb71a20fb5f947cebe0476625322f636c2ddb65 100644 (file)
--- a/lib/Target/ARM64/ARM64InstrFormats.td
+++ b/lib/Target/ARM64/ARM64InstrFormats.td
@@ -1603,6 +1603,8 @@ multiclass ExtractImm<string asm> {
                         (ARM64Extr GPR32:$Rn, GPR32:$Rm, imm0_31:$imm))]> {
     let Inst{31} = 0;
     let Inst{22} = 0;
+    // imm<5> must be zero.
+    let imm{5}   = 0;
   }
   def Xrri : BaseExtractImm<GPR64, imm0_63, asm,
                       [(set GPR64:$Rd,
@@ -4849,7 +4851,9 @@ class BaseSIMDBitwiseExtract<bit size, RegisterOperand regtype, ValueType vty,
 
 
 multiclass SIMDBitwiseExtract<string asm> {
-  def v8i8  : BaseSIMDBitwiseExtract<0, V64, v8i8, asm, ".8b">;
+  def v8i8  : BaseSIMDBitwiseExtract<0, V64, v8i8, asm, ".8b"> {
+    let imm{3} = 0;
+  }
   def v16i8 : BaseSIMDBitwiseExtract<1, V128, v16i8, asm, ".16b">;
 }
 

diff --git a/test/MC/Disassembler/ARM64/basic-a64-undefined.txt b/test/MC/Disassembler/ARM64/basic-a64-undefined.txt
index 21ff82ccccf9de3e2a63b082261b10f0b3e53618..c2e3841bb944c3fc0b5e424fb1985a22e556089b 100644 (file)
--- a/test/MC/Disassembler/ARM64/basic-a64-undefined.txt
+++ b/test/MC/Disassembler/ARM64/basic-a64-undefined.txt
@@ -20,4 +20,7 @@
 # UBFM is undefined when s == 0 and imms<5> or immr<5> is 1.
 # RUN: echo "0x00 0x80 0x00 0x53" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
 
+# EXT on vectors of i8 must have imm<3> = 0.
+# RUN: echo "0x00 0x40 0x00 0x2e" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
+
 # CHECK: invalid instruction encoding