In lowering SELECT_CC, removed cases where we can't flip the true and false when...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55499 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 9472cee028c9eed1ea57f8ed81f90038292ae004..5c69085ef2c1bc976200360848150b1752aabd6a 100644 (file)
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -2734,20 +2734,16 @@ SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
     switch (CC) {
     default: break;       // SETUO etc aren't handled by fsel.
     case ISD::SETULT:
-    case ISD::SETOLT:
     case ISD::SETLT:
       std::swap(TV, FV);  // fsel is natively setge, swap operands for setlt
-    case ISD::SETUGE:
     case ISD::SETOGE:
     case ISD::SETGE:
       if (LHS.getValueType() == MVT::f32)   // Comparison is always 64-bits
         LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
       return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
     case ISD::SETUGT:
-    case ISD::SETOGT:
     case ISD::SETGT:
       std::swap(TV, FV);  // fsel is natively setge, swap operands for setlt
-    case ISD::SETULE:
     case ISD::SETOLE:
     case ISD::SETLE:
       if (LHS.getValueType() == MVT::f32)   // Comparison is always 64-bits
@@ -2760,13 +2756,11 @@ SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
   switch (CC) {
   default: break;       // SETUO etc aren't handled by fsel.
   case ISD::SETULT:
-  case ISD::SETOLT:
   case ISD::SETLT:
     Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
     if (Cmp.getValueType() == MVT::f32)   // Comparison is always 64-bits
       Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
       return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
-  case ISD::SETUGE:
   case ISD::SETOGE:
   case ISD::SETGE:
     Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
@@ -2774,13 +2768,11 @@ SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
       Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
       return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
   case ISD::SETUGT:
-  case ISD::SETOGT:
   case ISD::SETGT:
     Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
     if (Cmp.getValueType() == MVT::f32)   // Comparison is always 64-bits
       Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
       return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
-  case ISD::SETULE:
   case ISD::SETOLE:
   case ISD::SETLE:
     Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);

diff --git a/test/CodeGen/PowerPC/fnegsel.ll b/test/CodeGen/PowerPC/fnegsel.ll
index c223a496abdf1aa674f79a1a7b49d9d60b62d88e..62ed4dde0761411a2002ee37a8ab8962db5d1243 100644 (file)
--- a/test/CodeGen/PowerPC/fnegsel.ll
+++ b/test/CodeGen/PowerPC/fnegsel.ll
@@ -2,7 +2,7 @@
 
 define double @test_FNEG_sel(double %A, double %B, double %C) {
         %D = sub double -0.000000e+00, %A               ; <double> [#uses=1]
-        %Cond = fcmp ogt double %D, -0.000000e+00               ; <i1> [#uses=1]
+        %Cond = fcmp ugt double %D, -0.000000e+00               ; <i1> [#uses=1]
         %E = select i1 %Cond, double %B, double %C              ; <double> [#uses=1]
         ret double %E
 }