ARM: dts: imx27-phytec-phycard-s-som: Rename file to .dtsi

PCA-100 module cannot be used standalone. This patch renames
module file to .dtsi and excludes it from compilation.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 77f653648e61721854dbfa97a1b74607ed6417ab..b7b40675e54f1a5e0eda485489ba5213b52baf90 100644 (file)
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -140,7 +140,6 @@ dtb-$(CONFIG_ARCH_MXC) += \
        imx27-apf27dev.dtb \
        imx27-pdk.dtb \
        imx27-phytec-phycore-rdk.dtb \
-       imx27-phytec-phycard-s-som.dtb \
        imx27-phytec-phycard-s-rdk.dtb \
        imx31-bug.dtb \
        imx35-eukrea-mbimxsd35-baseboard.dtb \

diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
index 1cd3a879dc85651b6ec174ef5a4b60d70328d012..3c3964a996376e6aa125adb72784b7ebd40fba70 100644 (file)
--- a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
@@ -9,7 +9,7 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-#include "imx27-phytec-phycard-s-som.dts"
+#include "imx27-phytec-phycard-s-som.dtsi"
 
 / {
        model = "Phytec pca100 rapid development kit";

diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts
deleted file mode 100644 (file)
index 1b62480..0000000
--- a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * Copyright 2012 Sascha Hauer, Uwe Kleine-König, Steffen Trumtrar
- * and Markus Pargmann, Pengutronix
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/dts-v1/;
-#include "imx27.dtsi"
-
-/ {
-       model = "Phytec pca100";
-       compatible = "phytec,imx27-pca100", "fsl,imx27";
-
-       memory {
-               reg = <0xa0000000 0x08000000>; /* 128MB */
-       };
-};
-
-&cspi1 {
-       fsl,spi-num-chipselects = <2>;
-       cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>,
-                  <&gpio4 27 GPIO_ACTIVE_HIGH>;
-       status = "okay";
-};
-
-&fec {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_fec1>;
-       status = "okay";
-};
-
-&i2c2 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_i2c2>;
-       status = "okay";
-
-       at24@52 {
-               compatible = "at,24c32";
-               pagesize = <32>;
-               reg = <0x52>;
-       };
-};
-
-&iomuxc {
-       imx27-phycard-s-som {
-               pinctrl_fec1: fec1grp {
-                       fsl,pins = <
-                               MX27_PAD_SD3_CMD__FEC_TXD0 0x0
-                               MX27_PAD_SD3_CLK__FEC_TXD1 0x0
-                               MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
-                               MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
-                               MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
-                               MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
-                               MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
-                               MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
-                               MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
-                               MX27_PAD_ATA_DATA7__FEC_MDC 0x0
-                               MX27_PAD_ATA_DATA8__FEC_CRS 0x0
-                               MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
-                               MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
-                               MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
-                               MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
-                               MX27_PAD_ATA_DATA13__FEC_COL 0x0
-                               MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
-                               MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
-                       >;
-               };
-
-               pinctrl_i2c2: i2c2grp {
-                       fsl,pins = <
-                               MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
-                               MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
-                       >;
-               };
-
-               pinctrl_nfc: nfcgrp {
-                       fsl,pins = <
-                               MX27_PAD_NFRB__NFRB 0x0
-                               MX27_PAD_NFCLE__NFCLE 0x0
-                               MX27_PAD_NFWP_B__NFWP_B 0x0
-                               MX27_PAD_NFCE_B__NFCE_B 0x0
-                               MX27_PAD_NFALE__NFALE 0x0
-                               MX27_PAD_NFRE_B__NFRE_B 0x0
-                               MX27_PAD_NFWE_B__NFWE_B 0x0
-                       >;
-               };
-       };
-};
-
-&nfc {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_nfc>;
-       nand-bus-width = <8>;
-       nand-ecc-mode = "hw";
-       nand-on-flash-bbt;
-       status = "okay";
-};

diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi
new file mode 100644 (file)
index 0000000..1b62480
--- /dev/null
+++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi
@@ -0,0 +1,103 @@
+/*
+ * Copyright 2012 Sascha Hauer, Uwe Kleine-König, Steffen Trumtrar
+ * and Markus Pargmann, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include "imx27.dtsi"
+
+/ {
+       model = "Phytec pca100";
+       compatible = "phytec,imx27-pca100", "fsl,imx27";
+
+       memory {
+               reg = <0xa0000000 0x08000000>; /* 128MB */
+       };
+};
+
+&cspi1 {
+       fsl,spi-num-chipselects = <2>;
+       cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>,
+                  <&gpio4 27 GPIO_ACTIVE_HIGH>;
+       status = "okay";
+};
+
+&fec {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_fec1>;
+       status = "okay";
+};
+
+&i2c2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c2>;
+       status = "okay";
+
+       at24@52 {
+               compatible = "at,24c32";
+               pagesize = <32>;
+               reg = <0x52>;
+       };
+};
+
+&iomuxc {
+       imx27-phycard-s-som {
+               pinctrl_fec1: fec1grp {
+                       fsl,pins = <
+                               MX27_PAD_SD3_CMD__FEC_TXD0 0x0
+                               MX27_PAD_SD3_CLK__FEC_TXD1 0x0
+                               MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
+                               MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
+                               MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
+                               MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
+                               MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
+                               MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
+                               MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
+                               MX27_PAD_ATA_DATA7__FEC_MDC 0x0
+                               MX27_PAD_ATA_DATA8__FEC_CRS 0x0
+                               MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
+                               MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
+                               MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
+                               MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
+                               MX27_PAD_ATA_DATA13__FEC_COL 0x0
+                               MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
+                               MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
+                       >;
+               };
+
+               pinctrl_i2c2: i2c2grp {
+                       fsl,pins = <
+                               MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
+                               MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
+                       >;
+               };
+
+               pinctrl_nfc: nfcgrp {
+                       fsl,pins = <
+                               MX27_PAD_NFRB__NFRB 0x0
+                               MX27_PAD_NFCLE__NFCLE 0x0
+                               MX27_PAD_NFWP_B__NFWP_B 0x0
+                               MX27_PAD_NFCE_B__NFCE_B 0x0
+                               MX27_PAD_NFALE__NFALE 0x0
+                               MX27_PAD_NFRE_B__NFRE_B 0x0
+                               MX27_PAD_NFWE_B__NFWE_B 0x0
+                       >;
+               };
+       };
+};
+
+&nfc {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_nfc>;
+       nand-bus-width = <8>;
+       nand-ecc-mode = "hw";
+       nand-on-flash-bbt;
+       status = "okay";
+};