Missed a couple redundant explicit type casts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24684 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index a3c16c70ec863200c281185309fe72dec71ac93d..736b8a90d1d411e406b78378e7d778a1e8d14c28 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -354,15 +354,15 @@ def OUT32rr : I<0xEF, RawFrm, (ops),
 
 def OUT8ir  : Ii8<0xE6, RawFrm, (ops i16i8imm:$port),
                    "out{b} {%al, $port|$port, %AL}",
-                   [(writeport AL, (i16 i16immZExt8:$port))]>,
+                   [(writeport AL, i16immZExt8:$port)]>,
                    Imp<[AL], []>;
 def OUT16ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port),
                    "out{w} {%ax, $port|$port, %AX}",
-                   [(writeport AX, (i16 i16immZExt8:$port))]>,
+                   [(writeport AX, i16immZExt8:$port)]>,
                    Imp<[AX], []>, OpSize;
 def OUT32ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port),
                    "out{l} {%eax, $port|$port, %EAX}",
-                   [(writeport EAX, (i16 i16immZExt8:$port))]>,
+                   [(writeport EAX, i16immZExt8:$port)]>,
                    Imp<[EAX], []>;
 
 //===----------------------------------------------------------------------===//