SubRegIndex'ize MSP430

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104513 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/MSP430/MSP430RegisterInfo.td b/lib/Target/MSP430/MSP430RegisterInfo.td
index 4078626ea2ddda0f0ea8c13191bd345710ef25d2..db3f0e789abb039df95d717ea104ecd4aaba9641 100644 (file)
--- a/lib/Target/MSP430/MSP430RegisterInfo.td
+++ b/lib/Target/MSP430/MSP430RegisterInfo.td
@@ -65,7 +65,10 @@ def : SubRegSet<1, [PCW, SPW, SRW, CGW, FPW,
                    [PCB, SPB, SRB, CGB, FPB,
                     R5B, R6B, R7B, R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
 
-def subreg_8bit : PatLeaf<(i32 1)>;
+def subreg_8bit : SubRegIndex {
+  let NumberHack = 1;
+  let Namespace = "MSP430";
+}
 
 def GR8 : RegisterClass<"MSP430", [i8], 8,
    // Volatile registers