SDMMC: Add the judgment on soc differences between rk3188 and rk32XX
authorxbw <xbw@rock-chips.com>
Sat, 15 Mar 2014 09:36:32 +0000 (17:36 +0800)
committerxbw <xbw@rock-chips.com>
Sat, 15 Mar 2014 09:37:14 +0000 (17:37 +0800)
arch/arm/boot/dts/rk3188-mmc.dtsi
drivers/mmc/host/dw_mmc-rockchip.c
drivers/mmc/host/rk_sdmmc.c
drivers/mmc/host/rk_sdmmc.h
drivers/mmc/host/rk_sdmmc_of.h
include/linux/mmc/host.h
include/linux/mmc/rk_mmc.h

index 68817fb0f486cea7d4b8dbc370995643b236c957..3bf354a05649b0af1d9c03fcafd3785bc520f5f2 100755 (executable)
                supports-emmc;
                 bootpart-no-access;
                fifo-depth = <0x80>;
-
-                 
-               mmc,caps = <(MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED)>;
-               mmc,ocr =  <(MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
-                                    MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
-                                    MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36)>;
-               mmc,use_dma = <MMC_USE_DMA 2>;
-               mmc,dma_ch = <EMMC_DMA_CHN>;
-               mmc,int = <CONTROLLER_INT_DETECT>;
-               mmc,emmc_is_selected = <1>;
+               bus-width = <4>;
+     
+               //mmc,caps = <(MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED)>;
+       //      mmc,ocr =  <(MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
+       //                           MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
+       //                           MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36)>;
+       //      mmc,use_dma = <MMC_USE_DMA 2>;
+       //      mmc,dma_ch = <EMMC_DMA_CHN>;
+       //      mmc,int = <CONTROLLER_INT_DETECT>;
+       //        mmc,emmc_is_selected = <1>;
                status = "okay";
     };
        
            card-detect-delay = <200>;
            pwr-gpios = <&gpio3 GPIO_A1 GPIO_ACTIVE_LOW>; /*pwr_en = GPIO3_A1*/
            fifo-depth = <0x100>;
+               bus-width = <4>;
+           
            
-            mmc,caps = <(MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED)>;
-           mmc,ocr =  <(MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
-                                MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
-                                        MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36)>;
-           mmc,use_dma = <MMC_USE_DMA 0>; 
-           mmc,dma_ch = <SDMMC_DMA_CHN>;
-               mmc,int = <CONTROLLER_INT_DETECT>;      
-         //mmc,int = <GPIO_INT_DETECT>;
-           mmc,emmc_is_selected = <0>;
            status = "okay";
        };
 
@@ -99,6 +92,7 @@
            supports-highspeed;
             supports-sdio;
            fifo-depth = <0x100>;
+           bus-width = <4>;
            
             mmc,caps = <(MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED)>;
            mmc,ocr =  <(MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
          ////mmc,int = <GPIO_INT_DETECT>;
            ////OOB pin?
            //mmc,emmc_is_selected = <0>;
-           status = "okay";
+           status = "disabled";
        };
 
                                                                                                                                                                                                                                                                                                                                                                
index d62c3dc2eb77a5275969d69ef3c9731a5a451e16..fcaf5542d8662f0b0bd3a98a253a582c44e4dfc7 100755 (executable)
@@ -44,6 +44,7 @@
 
 /* Variations in Rockchip specific dw-mshc controller */
 enum dw_mci_rockchip_type {
+       DW_MCI_TYPE_RK3188,
        DW_MCI_TYPE_RK3288,
 };
 
@@ -60,6 +61,9 @@ static struct dw_mci_rockchip_compatible {
        enum dw_mci_rockchip_type               ctrl_type;
 } rockchip_compat[] = {
        {
+               .compatible     = "rockchip,rk3188-sdmmc",
+               .ctrl_type      = DW_MCI_TYPE_RK3188,
+       },{
                .compatible     = "rockchip,rk3288-sdmmc",
                .ctrl_type      = DW_MCI_TYPE_RK3288,
        },
@@ -156,14 +160,17 @@ static int dw_mci_rockchip_parse_dt(struct dw_mci *host)
 /* Common capabilities of RK32XX SoC */
 static unsigned long rockchip_dwmmc_caps[4] = {
        /*MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR | //Temporarily comment out!!!!!!, deleted by xbw, at 2014-03-12*/
-               MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
+               MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23|MMC_CAP_UHS_SDR12|MMC_CAP_UHS_SDR25|MMC_CAP_UHS_SDR50,
        MMC_CAP_CMD23,
        MMC_CAP_CMD23,
        MMC_CAP_CMD23,
 };
 
+unsigned int  rockchip_dwmmc_hold_reg[4] = {1,0,0,0};
+
 static const struct dw_mci_drv_data rockchip_drv_data = {
        .caps                   = rockchip_dwmmc_caps,
+       .hold_reg_flag  = rockchip_dwmmc_hold_reg,
        .init                   = dw_mci_rockchip_priv_init,
        .setup_clock            = dw_mci_rockchip_setup_clock,
        .prepare_command        = dw_mci_rockchip_prepare_command,
index 8b793cc51ac8a72e8c1634fc06856d2549d0ed66..4e27ed7063981713f182f4f5685c57ba7713e5b9 100755 (executable)
@@ -346,7 +346,10 @@ static void dw_mci_start_command(struct dw_mci *host,
     MMC_DBG_INFO_FUNC(host->mmc,"%d..%s start cmd=%d, arg=0x%x[%s]",__LINE__, __FUNCTION__,cmd->opcode, cmd->arg,mmc_hostname(host->mmc));
     //dw_mci_regs_printk(host);
 
-       mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START|SDMMC_CMD_USE_HOLD_REG); //always use SDMMC_CMD_USE_HOLD_REG 
+    if(host->mmc->hold_reg_flag)
+        cmd_flags |= SDMMC_CMD_USE_HOLD_REG;//fix the value to 1 in some Soc,for example RK3188.
+        
+       mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
 }
 
 static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
@@ -2246,7 +2249,7 @@ static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
 /* find out bus-width for a given slot */
 static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot)
 {
-       struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
+       struct device_node *np = dev->of_node;//dw_mci_of_find_slot_node(dev, slot);
        u32 bus_wd = 1;
 
        if (!np)
@@ -2427,6 +2430,8 @@ static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
        }
        if (drv_data && drv_data->caps)
                mmc->caps |= drv_data->caps[ctrl_id];
+       if (drv_data && drv_data->hold_reg_flag)
+               mmc->hold_reg_flag |= drv_data->hold_reg_flag[ctrl_id];         
 
        if (host->pdata->caps2)
                mmc->caps2 = host->pdata->caps2;
index 46db159f7b6619150d3a25e115fbb6aefa65a221..e0e92b980c40302b5da6293bb68088cb1b6076ed 100755 (executable)
@@ -304,6 +304,7 @@ struct dw_mci_tuning_data {
 /**
  * dw_mci driver data - dw-mshc implementation specific driver data.
  * @caps: mmc subsystem specified capabilities of the controller(s).
+ * @hold_reg_flag: Fixed the value of HOLG_REG
  * @init: early implementation specific initialization.
  * @setup_clock: implementation specific clock configuration.
  * @prepare_command: handle CMD register extensions.
@@ -316,6 +317,7 @@ struct dw_mci_tuning_data {
  */
 struct dw_mci_drv_data {
        unsigned long   *caps;
+       unsigned int    *hold_reg_flag;
        int             (*init)(struct dw_mci *host);
        int             (*setup_clock)(struct dw_mci *host);
        void            (*prepare_command)(struct dw_mci *host, u32 *cmdr);
index 28b4508b3a0f6e613b43a95dd7d5c9c7bd0994d2..da8b514718565240b5cf5e2de9523034621240d9 100755 (executable)
@@ -50,7 +50,7 @@ extern char dbg_flag[];
 #define MMC_DBG_ERR_FUNC(mmc_host,fmt, arg...) \\r
     do{ \\r
         if(mmc_debug_level >= MMC_DBG_ERROR) { \\r
-            if(NULL != strpbrk(dbg_flag,mmc_hostname(mmc_host))) { \\r
+            if(strstr(dbg_flag,mmc_hostname(mmc_host))) { \\r
                 printk(DRIVER_PREFIX "ERROR " fmt "\n", ##arg);\\r
             } \\r
         } \\r
@@ -58,7 +58,7 @@ extern char dbg_flag[];
 #define MMC_DBG_WARN_FUNC(mmc_host,fmt, arg...) \\r
     do { \\r
         if(mmc_debug_level >= MMC_DBG_WARN) { \\r
-            if(NULL != strpbrk(dbg_flag,mmc_hostname(mmc_host))) { \\r
+            if(strstr(dbg_flag,mmc_hostname(mmc_host))) { \\r
                 printk(DRIVER_PREFIX "WARN " fmt "\n", ##arg);\\r
             } \\r
         } \\r
@@ -66,7 +66,7 @@ extern char dbg_flag[];
 #define MMC_DBG_INFO_FUNC(mmc_host,fmt, arg...) \\r
     do { \\r
         if(mmc_debug_level >= MMC_DBG_INFO) { \\r
-            if(NULL != strpbrk(dbg_flag,mmc_hostname(mmc_host))) { \\r
+            if(strstr(dbg_flag,mmc_hostname(mmc_host))) { \\r
                 printk(DRIVER_PREFIX "INFO " fmt "\n", ##arg);\\r
             } \\r
         } \\r
@@ -74,7 +74,7 @@ extern char dbg_flag[];
 #define MMC_DBG_CMD_FUNC(mmc_host,fmt, arg...) \\r
    do { \\r
         if(mmc_debug_level >= MMC_DBG_CMD) { \\r
-            if(NULL != strpbrk(dbg_flag,mmc_hostname(mmc_host))) { \\r
+            if(strstr(dbg_flag,mmc_hostname(mmc_host))) { \\r
                 printk(DRIVER_PREFIX "CMD " fmt "\n", ##arg);\\r
             } \\r
         } \\r
@@ -83,7 +83,7 @@ extern char dbg_flag[];
 #define MMC_DBG_BOOT_FUNC(mmc_host,fmt, arg...) {printk(DRIVER_PREFIX "BOOT " fmt "\n", ##arg);}\r
 #define MMC_DBG_ERR_FUNC(mmc_host,fmt, arg...)\r
 #define MMC_DBG_WARN_FUNC(mmc_host,fmt, arg...)\r
-#define MMC_DBG_INFO_FUNC\r
+#define MMC_DBG_INFO_FUNC(mmc_host,fmt, arg...)\r
 #define MMC_DBG_CMD_FUNC(mmc_host,fmt, arg...)\r
 #endif\r
 \r
index c882e0075cd153ed94e328750234763263ec1a50..fd2a7075f76547af51f827569f7b31b981eb3bf9 100755 (executable)
@@ -290,6 +290,8 @@ struct mmc_host {
 #define RESTRICT_CARD_TYPE_SD  (1 << 0)        /*noted by XBW, Rockchip Co.Ld*/
 #define RESTRICT_CARD_TYPE_SDIO        (1 << 1)        
 #define RESTRICT_CARD_TYPE_EMMC        (1 << 2)        
+    unsigned int    hold_reg_flag;//to fix the hold_reg value
+
 
 #ifdef CONFIG_MMC_CLKGATE
        int                     clk_requests;   /* internal reference counter */
index fab2825da2f8559094f0d07bb0f1e45cc7fd5dcc..130b2ec80dbe5cbfa3c11ebfc62d0ad6db3659a4 100755 (executable)
@@ -173,6 +173,7 @@ struct dw_mci {
        struct dw_mci_slot      *slot[MAX_MCI_SLOTS];
        struct mmc_host         *mmc;
        struct mmc_command      *pre_cmd;
+       unsigned int    hold_reg_flag;//to fix the hold_reg value
 
        /* FIFO push and pull */
        int                     fifo_depth;