the floating point register mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194423
91177308-0d34-0410-b5e6-
96231b3b80d8
//
static bool useConstantIslands();
- unsigned stackAlignment() const { return isFP64bit() ? 16 : 8; }
+ unsigned stackAlignment() const { return hasMips64() ? 16 : 8; }
// Grab MipsRegInfo object
const MipsReginfo &getMReginfo() const { return MRI; }
; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=32
-; RUN: llc -march=mipsel -mattr=+fp64 < %s | FileCheck %s -check-prefix=32-FP64
+; RUN: llc -march=mipsel -mattr=+fp64 < %s | FileCheck %s -check-prefix=32
; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=64
; 32: addiu $sp, $sp, -8
-; 32-FP64: addiu $sp, $sp, -16
; 64: addiu $sp, $sp, -16
define i32 @foo1() #0 {