hdmi_msk_reg(hdmi_dev, AUD_CONF0,
m_SW_AUD_FIFO_RST, v_SW_AUD_FIFO_RST(1));
hdmi_writel(hdmi_dev, MC_SWRSTZREQ, 0xF7);
+ hdmi_writel(hdmi_dev, AUD_CONF2, 0x0);
usleep_range(90, 100);
+ if (I2S_CHANNEL_7_8 == channel) {
+ HDMIDBG("hbr mode.\n");
+ hdmi_writel(hdmi_dev, AUD_CONF2, 0x1);
+ word_length = I2S_24BIT_SAMPLE;
+ } else if ((HDMI_AUDIO_FS_48000 == audio->rate)
+ || (HDMI_AUDIO_FS_192000 == audio->rate)) {
+ HDMIDBG("nlpcm mode.\n");
+ hdmi_writel(hdmi_dev, AUD_CONF2, 0x2);
+ word_length = I2S_24BIT_SAMPLE;
+ } else {
+ hdmi_writel(hdmi_dev, AUD_CONF2, 0x0);
+ }
hdmi_msk_reg(hdmi_dev, AUD_CONF0,
m_I2S_SEL | m_I2S_IN_EN,
v_I2S_SEL(AUDIO_I2S) | v_I2S_IN_EN(channel));
#define I2S_CLR_ERROR_COUNT 10// check I2S_CLR reg
static struct rk30_i2s_info *rk30_i2s;
-#if defined (CONFIG_RK_HDMI) && defined (CONFIG_SND_RK_SOC_HDMI_I2S)
+#if 0 /*defined (CONFIG_RK_HDMI) && defined (CONFIG_SND_RK_SOC_HDMI_I2S)*/
extern int hdmi_get_hotplug(void);
#else
#define hdmi_get_hotplug() 0
i2s->playback_dma_data.addr = regs_base + I2S_TXR_BUFF;
i2s->playback_dma_data.addr_width = 4;
- i2s->playback_dma_data.maxburst = 1;
+ i2s->playback_dma_data.maxburst = 16;
i2s->capture_dma_data.addr = regs_base + I2S_RXR_BUFF;
i2s->capture_dma_data.addr_width = 4;
- i2s->capture_dma_data.maxburst = 1;
+ i2s->capture_dma_data.maxburst = 16;
i2s->i2s_tx_status = false;
i2s->i2s_rx_status = false;