Fix the operand ordering on aliases for shld and shrd. PR12173, part 2.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152136 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index f585b476630697498f4a6e229eb9e6af0038b5ed..dd7cf500cb1c6a08ef7e8437a059996666b4813f 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -1856,19 +1856,19 @@ def : InstAlias<"outl $port", (OUT32ir i8imm:$port)>;
 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem)>;
 
 // shld/shrd op,op -> shld op, op, CL
-def : InstAlias<"shldw $r1, $r2", (SHLD16rrCL GR16:$r1, GR16:$r2)>;
-def : InstAlias<"shldl $r1, $r2", (SHLD32rrCL GR32:$r1, GR32:$r2)>;
-def : InstAlias<"shldq $r1, $r2", (SHLD64rrCL GR64:$r1, GR64:$r2)>;
-def : InstAlias<"shrdw $r1, $r2", (SHRD16rrCL GR16:$r1, GR16:$r2)>;
-def : InstAlias<"shrdl $r1, $r2", (SHRD32rrCL GR32:$r1, GR32:$r2)>;
-def : InstAlias<"shrdq $r1, $r2", (SHRD64rrCL GR64:$r1, GR64:$r2)>;
-
-def : InstAlias<"shldw $mem, $reg", (SHLD16mrCL i16mem:$mem, GR16:$reg)>;
-def : InstAlias<"shldl $mem, $reg", (SHLD32mrCL i32mem:$mem, GR32:$reg)>;
-def : InstAlias<"shldq $mem, $reg", (SHLD64mrCL i64mem:$mem, GR64:$reg)>;
-def : InstAlias<"shrdw $mem, $reg", (SHRD16mrCL i16mem:$mem, GR16:$reg)>;
-def : InstAlias<"shrdl $mem, $reg", (SHRD32mrCL i32mem:$mem, GR32:$reg)>;
-def : InstAlias<"shrdq $mem, $reg", (SHRD64mrCL i64mem:$mem, GR64:$reg)>;
+def : InstAlias<"shldw $r2, $r1", (SHLD16rrCL GR16:$r1, GR16:$r2)>;
+def : InstAlias<"shldl $r2, $r1", (SHLD32rrCL GR32:$r1, GR32:$r2)>;
+def : InstAlias<"shldq $r2, $r1", (SHLD64rrCL GR64:$r1, GR64:$r2)>;
+def : InstAlias<"shrdw $r2, $r1", (SHRD16rrCL GR16:$r1, GR16:$r2)>;
+def : InstAlias<"shrdl $r2, $r1", (SHRD32rrCL GR32:$r1, GR32:$r2)>;
+def : InstAlias<"shrdq $r2, $r1", (SHRD64rrCL GR64:$r1, GR64:$r2)>;
+
+def : InstAlias<"shldw $reg, $mem", (SHLD16mrCL i16mem:$mem, GR16:$reg)>;
+def : InstAlias<"shldl $reg, $mem", (SHLD32mrCL i32mem:$mem, GR32:$reg)>;
+def : InstAlias<"shldq $reg, $mem", (SHLD64mrCL i64mem:$mem, GR64:$reg)>;
+def : InstAlias<"shrdw $reg, $mem", (SHRD16mrCL i16mem:$mem, GR16:$reg)>;
+def : InstAlias<"shrdl $reg, $mem", (SHRD32mrCL i32mem:$mem, GR32:$reg)>;
+def : InstAlias<"shrdq $reg, $mem", (SHRD64mrCL i64mem:$mem, GR64:$reg)>;
 
 /*  FIXME: This is disabled because the asm matcher is currently incapable of
  *  matching a fixed immediate like $1.

diff --git a/test/MC/X86/x86-64.s b/test/MC/X86/x86-64.s
index d5e1b9c20b1d8f738eb01f6cc4863fc521f406df..308bb055fb46b5ab8d1e81468d0390c7d7e26fa1 100644 (file)
--- a/test/MC/X86/x86-64.s
+++ b/test/MC/X86/x86-64.s
@@ -340,19 +340,27 @@ rclb      $2, %bl   // CHECK: rclb $2, %bl # encoding: [0xc0,0xd3,0x02]
 
 // rdar://8418316
 // PR12173
-// CHECK: shldw        %cl, %bx, %bx
-// CHECK: shldw        %cl, %bx, %bx
-// CHECK: shldw        $1, %bx, %bx
-// CHECK: shrdw        %cl, %bx, %bx
-// CHECK: shrdw        %cl, %bx, %bx
-// CHECK: shrdw        $1, %bx, %bx
-
-shld  %bx, %bx
-shld  %cl, %bx, %bx
-shld  $1, %bx, %bx
-shrd  %bx, %bx
-shrd  %cl, %bx, %bx
-shrd  $1, %bx, %bx
+// CHECK: shldw        %cl, %bx, %dx
+// CHECK: shldw        %cl, %bx, %dx
+// CHECK: shldw        $1, %bx, %dx
+// CHECK: shldw        %cl, %bx, (%rax)
+// CHECK: shldw        %cl, %bx, (%rax)
+// CHECK: shrdw        %cl, %bx, %dx
+// CHECK: shrdw        %cl, %bx, %dx
+// CHECK: shrdw        $1, %bx, %dx
+// CHECK: shrdw        %cl, %bx, (%rax)
+// CHECK: shrdw        %cl, %bx, (%rax)
+
+shld  %bx, %dx
+shld  %cl, %bx, %dx
+shld  $1, %bx, %dx
+shld  %bx, (%rax)
+shld  %cl, %bx, (%rax)
+shrd  %bx, %dx
+shrd  %cl, %bx, %dx
+shrd  $1, %bx, %dx
+shrd  %bx, (%rax)
+shrd  %cl, %bx, (%rax)
 
 // CHECK: sldtl        %ecx
 // CHECK: encoding: [0x0f,0x00,0xc1]