ARM: tegra: Use lower-case hexadecimal digits
authorThierry Reding <treding@nvidia.com>
Wed, 29 Apr 2015 11:53:21 +0000 (13:53 +0200)
committerThierry Reding <treding@nvidia.com>
Mon, 4 May 2015 11:25:19 +0000 (13:25 +0200)
For consistency with other device tree content, use lower-case
hexadecimal digits in register region specifications.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt
arch/arm/boot/dts/tegra124.dtsi
arch/arm/boot/dts/tegra20.dtsi

index 23e1d3194174abe27f5dcf12a784ecaee1146df1..41372d441131aa66071a13357413d752d1025138 100644 (file)
@@ -29,7 +29,7 @@ Example:
 
        fuse@7000f800 {
                compatible = "nvidia,tegra20-efuse";
-               reg = <0x7000F800 0x400>,
+               reg = <0x7000f800 0x400>,
                      <0x70000000 0x400>;
                clocks = <&tegra_car TEGRA20_CLK_FUSE>;
                clock-names = "fuse";
index cf01c818b8ea41999f231f07211aec46a86e505c..0d9f9ae73149a5722759248f3b07f47d58270c5c 100644 (file)
        apbmisc@0,70000800 {
                compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
                reg = <0x0 0x70000800 0x0 0x64>,   /* Chip revision */
-                     <0x0 0x7000E864 0x0 0x04>;   /* Strapping options */
+                     <0x0 0x7000e864 0x0 0x04>;   /* Strapping options */
        };
 
        pinmux: pinmux@0,70000868 {
index adf6b048d0bb52b5355f26eb06f79212a2e34cde..f444b67f55c6becc04f33b2748ba5f28eb994d6c 100644 (file)
 
        fuse@7000f800 {
                compatible = "nvidia,tegra20-efuse";
-               reg = <0x7000F800 0x400>;
+               reg = <0x7000f800 0x400>;
                clocks = <&tegra_car TEGRA20_CLK_FUSE>;
                clock-names = "fuse";
                resets = <&tegra_car 39>;