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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157020 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/MachineScheduler.cpp b/lib/CodeGen/MachineScheduler.cpp
index 0aaef5d59996b76004a1a8ba8e43d5a4871642f8..207d65a6b9468c5b299c6f0f34a88daf47d04aff 100644 (file)
--- a/lib/CodeGen/MachineScheduler.cpp
+++ b/lib/CodeGen/MachineScheduler.cpp
@@ -1,4 +1,4 @@
-//===- MachineScheduler.cpp - Machine Instruction Scheduler ---------------===//excess
+//===- MachineScheduler.cpp - Machine Instruction Scheduler ---------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -808,7 +808,8 @@ traceCandidate(const char *Label, unsigned QID, SUnit *SU,
 }
 #endif
 
-/// Return true if the LHS reg pressure effect is better than RHS.
+/// pickNodeFromQueue helper that returns true if the LHS reg pressure effect is
+/// more desirable than RHS from scheduling standpoint.
 static bool compareRPDelta(const RegPressureDelta &LHS,
                            const RegPressureDelta &RHS) {
   // Compare each component of pressure in decreasing order of importance