ARM64: dts: rk3368: Add iommu node for ISP/HEVC/VOP/VPU

Change-Id: I8193fa6f4cf186c2122b56d652f076024f517fb7
Signed-off-by: Simon <xxm@rock-chips.com>

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index ac1c4cdff88276851bf0217800d11daf8ae2c905..1d26f1b1aa34b4c2bb67c296a8e8ef3199576c45 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -975,6 +975,53 @@
                status = "disabled";
        };
 
+       isp_mmu: iommu@ff914000 {
+               compatible = "rockchip,iommu";
+               reg = <0x0 0xff914000 0x0 0x100>,
+                     <0x0 0xff915000 0x0 0x100>;
+               interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "isp_mmu";
+               #iommu-cells = <0>;
+               status = "disabled";
+       };
+
+       vop_mmu: iommu@ff930300 {
+               compatible = "rockchip,iommu";
+               reg = <0x0 0xff930300 0x0 0x100>;
+               interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "vop_mmu";
+               clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
+               clock-names = "aclk", "hclk";
+               power-domains = <&power RK3368_PD_VIO>;
+               #iommu-cells = <0>;
+               status = "disabled";
+       };
+
+       hevc_mmu: iommu@ff9a0440 {
+               compatible = "rockchip,iommu";
+               reg = <0x0 0xff9a0440 0x0 0x100>,
+                     <0x0 0xff9a0480 0x0 0x100>;
+               interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "hevc_mmu";
+               clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
+               clock-names = "aclk", "hclk";
+               power-domains = <&power RK3368_PD_VIDEO>;
+               #iommu-cells = <0>;
+               status = "disabled";
+       };
+
+       vpu_mmu: iommu@ff9a0800 {
+               compatible = "rockchip,iommu";
+               reg = <0x0 0xff9a0800 0x0 0x100>;
+               interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "vpu_mmu";
+               clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
+               clock-names = "aclk", "hclk";
+               power-domains = <&power RK3368_PD_VIDEO>;
+               #iommu-cells = <0>;
+               status = "disabled";
+       };
+
        gic: interrupt-controller@ffb71000 {
                compatible = "arm,gic-400";
                interrupt-controller;