Make this test less sensitive.

It currently assumes register numbering and any harmless change in the X86
register naming makes it fail. It's enough to match the register names.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168632 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/MC/Disassembler/X86/enhanced.txt b/test/MC/Disassembler/X86/enhanced.txt
index deff735b69dbc9563dd0e2729b6ecc3c77725115..97b0fa4ab5c89f6311297f90b04551e80b12e4d9 100644 (file)
--- a/test/MC/Disassembler/X86/enhanced.txt
+++ b/test/MC/Disassembler/X86/enhanced.txt
@@ -1,10 +1,10 @@
 # RUN: llvm-mc --edis %s -triple=x86_64-apple-darwin9 2>&1 | FileCheck %s
 
-# CHECK: [o:jne][w:    ][0-p:-][0-l:10=10] <br> 0:[RIP/112](pc)=18446744073709551606
+# CHECK: [o:jne][w:    ][0-p:-][0-l:10=10] <br> 0:[RIP/{{[0-9]+}}](pc)=18446744073709551606
 0x0f 0x85 0xf6 0xff 0xff 0xff
-# CHECK: [o:movq][w:   ][1-r:%gs=r64][1-p::][1-l:8=8][p:,][w: ][0-r:%rcx=r109] <mov> 0:[RCX/109]=0 1:[GS/64]=8
+# CHECK: [o:movq][w:   ][1-r:%gs=r{{[0-9]+}}][1-p::][1-l:8=8][p:,][w: ][0-r:%rcx=r{{[0-9]+}}] <mov> 0:[RCX/{{[0-9]+}}]=0 1:[GS/{{[0-9]+}}]=8
 0x65 0x48 0x8b 0x0c 0x25 0x08 0x00 0x00 0x00
-# CHECK: [o:xorps][w:  ][2-r:%xmm1=r130][p:,][w: ][0-r:%xmm2=r131] 0:[XMM2/131]=0 1:[XMM2/131]=0 2:[XMM1/130]=0
+# CHECK: [o:xorps][w:  ][2-r:%xmm1=r{{[0-9]+}}][p:,][w: ][0-r:%xmm2=r{{[0-9]+}}] 0:[XMM2/{{[0-9]+}}]=0 1:[XMM2/{{[0-9]+}}]=0 2:[XMM1/{{[0-9]+}}]=0
 0x0f 0x57 0xd1
-# CHECK: [o:andps][w:  ][2-r:%xmm1=r130][p:,][w: ][0-r:%xmm2=r131] 0:[XMM2/131]=0 1:[XMM2/131]=0 2:[XMM1/130]=0
+# CHECK: [o:andps][w:  ][2-r:%xmm1=r{{[0-9]+}}][p:,][w: ][0-r:%xmm2=r{{[0-9]+}}] 0:[XMM2/{{[0-9]+}}]=0 1:[XMM2/{{[0-9]+}}]=0 2:[XMM1/{{[0-9]+}}]=0
 0x0f 0x54 0xd1