}
break;
}
+ case TargetLowering::Custom:
+ Result = TLI.LowerOperation(Op, DAG);
+ if (Result.getNode())
+ break;
case TargetLowering::Legal: {
LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
if (Action == Legal && Tmp1 == Node->getOperand(0))
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Support/Mangler.h"
+#include "llvm/CodeGen/DwarfWriter.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
using namespace llvm;
// The processor should be passed to llc as in input and the header file
// should be generated accordingly.
O << "\t#include P16F1937.INC\n";
+ MachineModuleInfo *MMI = getAnalysisIfAvailable<MachineModuleInfo>();
+ assert(MMI);
+ DwarfWriter *DW = getAnalysisIfAvailable<DwarfWriter>();
+ assert(DW && "Dwarf Writer is not available");
+ DW->BeginModule(&M, MMI, O, this, TAI);
+
EmitExternsAndGlobals (M);
EmitInitData (M);
EmitUnInitData(M);
//setOperationAction(ISD::TRUNCATE, MVT::i16, Custom);
setTruncStoreAction(MVT::i16, MVT::i8, Custom);
+ setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Custom);
+
// Now deduce the information based on the above mentioned
// actions
computeRegisterProperties();
case PIC16ISD::SELECT_ICC: return "PIC16ISD::SELECT_ICC";
case PIC16ISD::BRCOND: return "PIC16ISD::BRCOND";
case PIC16ISD::Dummy: return "PIC16ISD::Dummy";
+ case PIC16ISD::PIC16StopPoint: return "PIC16ISD::PIC16StopPoint";
}
}
return LowerBR_CC(Op, DAG);
case ISD::SELECT_CC:
return LowerSELECT_CC(Op, DAG);
+ case ISD::DBG_STOPPOINT:
+ return LowerStopPoint(Op, DAG);
}
return SDValue();
}
+SDValue PIC16TargetLowering::LowerStopPoint(SDValue Op, SelectionDAG &DAG) {
+ DbgStopPointSDNode *SP = dyn_cast<DbgStopPointSDNode>(Op);
+ unsigned line = SP->getLine();
+ SDValue LineNode = DAG.getConstant(line, MVT::i8);
+ DebugLoc dl = Op.getDebugLoc();
+ return DAG.getNode(PIC16ISD::PIC16StopPoint, dl, MVT::Other,
+ Op.getOperand(0), LineNode);
+}
+
SDValue PIC16TargetLowering::ConvertToMemOperand(SDValue Op,
SelectionDAG &DAG,
DebugLoc dl) {
SUBCC, // Compare for equality or inequality.
SELECT_ICC, // Psuedo to be caught in schedular and expanded to brcond.
BRCOND, // Conditional branch.
+ PIC16StopPoint,
Dummy
};
SDValue InFlag, SelectionDAG &DAG);
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG);
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerStopPoint(SDValue Op, SelectionDAG &DAG);
SDValue getPIC16Cmp(SDValue LHS, SDValue RHS, unsigned OrigCC, SDValue &CC,
SelectionDAG &DAG, DebugLoc dl);
virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
def PIC16callseq_end : SDNode<"ISD::CALLSEQ_END", SDTI8VoidOp,
[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
+def PIC16StopPoint : SDNode<"PIC16ISD::PIC16StopPoint", SDTI8VoidOp,
+ [SDNPHasChain]>;
+
// Low 8-bits of GlobalAddress.
def PIC16Lo : SDNode<"PIC16ISD::Lo", SDTI8UnaryOp>;
// PIC16 Instructions.
//===----------------------------------------------------------------------===//
+def line_directive : ByteFormat<0, (outs), (ins i8imm:$src),
+ ".line $src",
+ [(PIC16StopPoint (i8 imm:$src))]>;
+
// Pseudo-instructions.
def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i8imm:$amt),
"!ADJCALLSTACKDOWN $amt",