Temporarily revert 48175.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48204 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp
index 144f0a7d430f6ae500009b9c18aae82a8b1fb737..d43cc19683c4a4be86b823f2e0c7416ca1e4d26e 100644 (file)
--- a/lib/CodeGen/RegAllocLinearScan.cpp
+++ b/lib/CodeGen/RegAllocLinearScan.cpp
@@ -685,14 +685,8 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
     }
 
     // All registers must have inf weight. Just grab one!
-    if (!minReg) {
-      if (active_.size() == 0) {
-        // FIXME: All the registers are occupied by fixed intervals.
-        cerr << "Register allocator ran out of registers!\n";
-        abort();
-      }
+    if (!minReg)
       minReg = *RC->allocation_order_begin(*mf_);
-    }
   }
   
   DOUT << "\t\tregister with min weight: "