ARM: OMAP2+: clock/dpll: convert bypass check to use clk_features
authorTero Kristo <t-kristo@ti.com>
Wed, 2 Jul 2014 08:47:42 +0000 (11:47 +0300)
committerPaul Walmsley <paul@pwsan.com>
Tue, 15 Jul 2014 20:09:06 +0000 (14:09 -0600)
OMAP2 DPLL code for checking whether DPLL is in bypass mode now uses
clk_features data provided during boot. This avoids the need to use
cpu_is_X type checks runtime, and allows us to eventually move the
clock code under the clock driver.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
arch/arm/mach-omap2/clkt_dpll.c
arch/arm/mach-omap2/clock.c
arch/arm/mach-omap2/clock.h

index 098e0893a6a610ca7e885dc2b969cbad7dce1fa5..49333d055f54af0858cdcd51c3fd8b442d7b86b3 100644 (file)
@@ -184,18 +184,19 @@ static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
  */
 static int _omap2_dpll_is_in_bypass(u32 v)
 {
-       if (cpu_is_omap24xx()) {
-               if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
-                   v == OMAP2XXX_EN_DPLL_FRBYPASS)
-                       return 1;
-       } else if (cpu_is_omap34xx()) {
-               if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
-                   v == OMAP3XXX_EN_DPLL_FRBYPASS)
-                       return 1;
-       } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) {
-               if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
-                   v == OMAP4XXX_EN_DPLL_FRBYPASS ||
-                   v == OMAP4XXX_EN_DPLL_MNBYPASS)
+       u8 mask, val;
+
+       mask = ti_clk_features.dpll_bypass_vals;
+
+       /*
+        * Each set bit in the mask corresponds to a bypass value equal
+        * to the bitshift. Go through each set-bit in the mask and
+        * compare against the given register value.
+        */
+       while (mask) {
+               val = __ffs(mask);
+               mask ^= (1 << val);
+               if (v == val)
                        return 1;
        }
 
index 7efe66e3a029af6f251163759cd5b8c99f46aa27..e4384377d9f812006387c9b2c428ea3299a01d42 100644 (file)
@@ -767,4 +767,21 @@ void __init ti_clk_init_features(void)
                ti_clk_features.fint_min = OMAP3PLUS_DPLL_FINT_MIN;
                ti_clk_features.fint_max = OMAP3PLUS_DPLL_FINT_MAX;
        }
+
+       /* Bypass value setup for DPLLs */
+       if (cpu_is_omap24xx()) {
+               ti_clk_features.dpll_bypass_vals |=
+                       (1 << OMAP2XXX_EN_DPLL_LPBYPASS) |
+                       (1 << OMAP2XXX_EN_DPLL_FRBYPASS);
+       } else if (cpu_is_omap34xx()) {
+               ti_clk_features.dpll_bypass_vals |=
+                       (1 << OMAP3XXX_EN_DPLL_LPBYPASS) |
+                       (1 << OMAP3XXX_EN_DPLL_FRBYPASS);
+       } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx() ||
+                  soc_is_omap54xx() || soc_is_dra7xx()) {
+               ti_clk_features.dpll_bypass_vals |=
+                       (1 << OMAP4XXX_EN_DPLL_LPBYPASS) |
+                       (1 << OMAP4XXX_EN_DPLL_FRBYPASS) |
+                       (1 << OMAP4XXX_EN_DPLL_MNBYPASS);
+       }
 }
index 02aa2e3ac03626d343eca6fdb5833edbf8763835..7b2b099c6a835112e57bd95e2bba45aca5e990d2 100644 (file)
@@ -232,6 +232,7 @@ struct ti_clk_features {
        long fint_max;
        long fint_band1_max;
        long fint_band2_min;
+       u8 dpll_bypass_vals;
 };
 extern struct ti_clk_features ti_clk_features;