R600/SI: Change formatting of printed FP immediates

Only 1 decimal place should be printed for inline immediates.
Other constants should be hex constants.

Does not include f64 tests because folding those inline
immediates currently does not work.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217964 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp b/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp
index d766b1002ea6a778a7ec36b3eec2135e8ddb4769..0aef956debacc3e7d70ee799cc3c2e9b4f05585c 100644 (file)
--- a/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp
+++ b/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp
@@ -182,19 +182,27 @@ void AMDGPUInstPrinter::printImmediate(uint32_t Imm, raw_ostream &O) {
     return;
   }
 
-  if (Imm == FloatToBits(1.0f) ||
-      Imm == FloatToBits(-1.0f) ||
-      Imm == FloatToBits(0.5f) ||
-      Imm == FloatToBits(-0.5f) ||
-      Imm == FloatToBits(2.0f) ||
-      Imm == FloatToBits(-2.0f) ||
-      Imm == FloatToBits(4.0f) ||
-      Imm == FloatToBits(-4.0f)) {
-    O << BitsToFloat(Imm);
-    return;
+  if (Imm == FloatToBits(0.0f))
+    O << "0.0";
+  else if (Imm == FloatToBits(1.0f))
+    O << "1.0";
+  else if (Imm == FloatToBits(-1.0f))
+    O << "-1.0";
+  else if (Imm == FloatToBits(0.5f))
+    O << "0.5";
+  else if (Imm == FloatToBits(-0.5f))
+    O << "-0.5";
+  else if (Imm == FloatToBits(2.0f))
+    O << "2.0";
+  else if (Imm == FloatToBits(-2.0f))
+    O << "-2.0";
+  else if (Imm == FloatToBits(4.0f))
+    O << "4.0";
+  else if (Imm == FloatToBits(-4.0f))
+    O << "-4.0";
+  else {
+    O << formatHex(static_cast<uint64_t>(Imm));
   }
-
-  O << formatHex(static_cast<uint64_t>(Imm));
 }
 
 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
@@ -214,7 +222,12 @@ void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
   } else if (Op.isImm()) {
     printImmediate(Op.getImm(), O);
   } else if (Op.isFPImm()) {
-    O << Op.getFPImm();
+
+    // We special case 0.0 because otherwise it will be printed as an integer.
+    if (Op.getFPImm() == 0.0)
+      O << "0.0";
+    else
+      printImmediate(FloatToBits(Op.getFPImm()), O);
   } else if (Op.isExpr()) {
     const MCExpr *Exp = Op.getExpr();
     Exp->print(O);

diff --git a/test/CodeGen/R600/fneg.ll b/test/CodeGen/R600/fneg.ll
index df61618259d644ff33039783a1e89b5eee708979..72cd15c7d70521d11b9315cb9691d42c970f0ff8 100644 (file)
--- a/test/CodeGen/R600/fneg.ll
+++ b/test/CodeGen/R600/fneg.ll
@@ -48,7 +48,7 @@ define void @fneg_v4f32(<4 x float> addrspace(1)* nocapture %out, <4 x float> %i
 ; R600: -KC0[2].Z
 
 ; XXX: We could use V_ADD_F32_e64 with the negate bit here instead.
-; SI: V_SUB_F32_e64 v{{[0-9]}}, 0.000000e+00, s{{[0-9]}}, 0, 0
+; SI: V_SUB_F32_e64 v{{[0-9]}}, 0.0, s{{[0-9]}}, 0, 0
 define void @fneg_free_f32(float addrspace(1)* %out, i32 %in) {
   %bc = bitcast i32 %in to float
   %fsub = fsub float 0.0, %bc

diff --git a/test/CodeGen/R600/imm.ll b/test/CodeGen/R600/imm.ll
index b047315be71a46dc582364ca4a6799abc4d281e1..e1d680c4ddb8ed4efd05cffef647c5ff9cb39cba 100644 (file)
--- a/test/CodeGen/R600/imm.ll
+++ b/test/CodeGen/R600/imm.ll
@@ -1,7 +1,7 @@
-; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
+; RUN: llc -march=r600 -mcpu=verde -verify-machineinstrs < %s | FileCheck %s
 
 ; Use a 64-bit value with lo bits that can be represented as an inline constant
-; CHECK: @i64_imm_inline_lo
+; CHECK-LABEL: @i64_imm_inline_lo
 ; CHECK: S_MOV_B32 [[LO:s[0-9]+]], 5
 ; CHECK: V_MOV_B32_e32 v[[LO_VGPR:[0-9]+]], [[LO]]
 ; CHECK: BUFFER_STORE_DWORDX2 v{{\[}}[[LO_VGPR]]:
@@ -12,7 +12,7 @@ entry:
 }
 
 ; Use a 64-bit value with hi bits that can be represented as an inline constant
-; CHECK: @i64_imm_inline_hi
+; CHECK-LABEL: @i64_imm_inline_hi
 ; CHECK: S_MOV_B32 [[HI:s[0-9]+]], 5
 ; CHECK: V_MOV_B32_e32 v[[HI_VGPR:[0-9]+]], [[HI]]
 ; CHECK: BUFFER_STORE_DWORDX2 v{{\[[0-9]+:}}[[HI_VGPR]]
@@ -21,3 +21,173 @@ entry:
   store i64 21780256376, i64 addrspace(1) *%out ; 0x0000000512345678
   ret void
 }
+
+; CHECK-LABEL: @store_inline_imm_0.0_f32
+; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], 0{{$}}
+; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
+define void @store_inline_imm_0.0_f32(float addrspace(1)* %out) {
+  store float 0.0, float addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: @store_inline_imm_0.5_f32
+; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], 0.5{{$}}
+; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
+define void @store_inline_imm_0.5_f32(float addrspace(1)* %out) {
+  store float 0.5, float addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: @store_inline_imm_m_0.5_f32
+; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], -0.5{{$}}
+; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
+define void @store_inline_imm_m_0.5_f32(float addrspace(1)* %out) {
+  store float -0.5, float addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: @store_inline_imm_1.0_f32
+; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], 1.0{{$}}
+; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
+define void @store_inline_imm_1.0_f32(float addrspace(1)* %out) {
+  store float 1.0, float addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: @store_inline_imm_m_1.0_f32
+; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], -1.0{{$}}
+; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
+define void @store_inline_imm_m_1.0_f32(float addrspace(1)* %out) {
+  store float -1.0, float addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: @store_inline_imm_2.0_f32
+; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], 2.0{{$}}
+; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
+define void @store_inline_imm_2.0_f32(float addrspace(1)* %out) {
+  store float 2.0, float addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: @store_inline_imm_m_2.0_f32
+; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], -2.0{{$}}
+; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
+define void @store_inline_imm_m_2.0_f32(float addrspace(1)* %out) {
+  store float -2.0, float addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: @store_inline_imm_4.0_f32
+; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], 4.0{{$}}
+; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
+define void @store_inline_imm_4.0_f32(float addrspace(1)* %out) {
+  store float 4.0, float addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: @store_inline_imm_m_4.0_f32
+; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], -4.0{{$}}
+; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
+define void @store_inline_imm_m_4.0_f32(float addrspace(1)* %out) {
+  store float -4.0, float addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: @store_literal_imm_f32
+; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], 0x45800000
+; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
+define void @store_literal_imm_f32(float addrspace(1)* %out) {
+  store float 4096.0, float addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: @add_inline_imm_0.0_f32
+; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
+; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], 0.0,
+; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
+define void @add_inline_imm_0.0_f32(float addrspace(1)* %out, float %x) {
+  %y = fadd float %x, 0.0
+  store float %y, float addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: @add_inline_imm_0.5_f32
+; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
+; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], 0.5,
+; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
+define void @add_inline_imm_0.5_f32(float addrspace(1)* %out, float %x) {
+  %y = fadd float %x, 0.5
+  store float %y, float addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: @add_inline_imm_neg_0.5_f32
+; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
+; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], -0.5,
+; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
+define void @add_inline_imm_neg_0.5_f32(float addrspace(1)* %out, float %x) {
+  %y = fadd float %x, -0.5
+  store float %y, float addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: @add_inline_imm_1.0_f32
+; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
+; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], 1.0,
+; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
+define void @add_inline_imm_1.0_f32(float addrspace(1)* %out, float %x) {
+  %y = fadd float %x, 1.0
+  store float %y, float addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: @add_inline_imm_neg_1.0_f32
+; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
+; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], -1.0,
+; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
+define void @add_inline_imm_neg_1.0_f32(float addrspace(1)* %out, float %x) {
+  %y = fadd float %x, -1.0
+  store float %y, float addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: @add_inline_imm_2.0_f32
+; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
+; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], 2.0,
+; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
+define void @add_inline_imm_2.0_f32(float addrspace(1)* %out, float %x) {
+  %y = fadd float %x, 2.0
+  store float %y, float addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: @add_inline_imm_neg_2.0_f32
+; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
+; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], -2.0,
+; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
+define void @add_inline_imm_neg_2.0_f32(float addrspace(1)* %out, float %x) {
+  %y = fadd float %x, -2.0
+  store float %y, float addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: @add_inline_imm_4.0_f32
+; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
+; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], 4.0,
+; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
+define void @add_inline_imm_4.0_f32(float addrspace(1)* %out, float %x) {
+  %y = fadd float %x, 4.0
+  store float %y, float addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: @add_inline_imm_neg_4.0_f32
+; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
+; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], -4.0,
+; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
+define void @add_inline_imm_neg_4.0_f32(float addrspace(1)* %out, float %x) {
+  %y = fadd float %x, -4.0
+  store float %y, float addrspace(1)* %out
+  ret void
+}

diff --git a/test/CodeGen/R600/insert_vector_elt.ll b/test/CodeGen/R600/insert_vector_elt.ll
index 43b4efc93377b6663a2d3264e714c5aec9e5fa2d..593ad1077b079feabd1a830f09f9cbd8a92cb79b 100644 (file)
--- a/test/CodeGen/R600/insert_vector_elt.ll
+++ b/test/CodeGen/R600/insert_vector_elt.ll
@@ -49,7 +49,7 @@ define void @insertelement_v4i32_0(<4 x i32> addrspace(1)* %out, <4 x i32> %a) n
 }
 
 ; SI-LABEL: @dynamic_insertelement_v2f32:
-; SI: V_MOV_B32_e32 [[CONST:v[0-9]+]], 5.000000e+00
+; SI: V_MOV_B32_e32 [[CONST:v[0-9]+]], 0x40a00000
 ; SI: V_MOVRELD_B32_e32 v[[LOW_RESULT_REG:[0-9]+]], [[CONST]]
 ; SI: BUFFER_STORE_DWORDX2 {{v\[}}[[LOW_RESULT_REG]]:
 define void @dynamic_insertelement_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, i32 %b) nounwind {
@@ -59,7 +59,7 @@ define void @dynamic_insertelement_v2f32(<2 x float> addrspace(1)* %out, <2 x fl
 }
 
 ; SI-LABEL: @dynamic_insertelement_v4f32:
-; SI: V_MOV_B32_e32 [[CONST:v[0-9]+]], 5.000000e+00
+; SI: V_MOV_B32_e32 [[CONST:v[0-9]+]], 0x40a00000
 ; SI: V_MOVRELD_B32_e32 v[[LOW_RESULT_REG:[0-9]+]], [[CONST]]
 ; SI: BUFFER_STORE_DWORDX4 {{v\[}}[[LOW_RESULT_REG]]:
 define void @dynamic_insertelement_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, i32 %b) nounwind {

diff --git a/test/CodeGen/R600/llvm.sin.ll b/test/CodeGen/R600/llvm.sin.ll
index 5b1f18e84b138564de8cb57dbcb325b15c34212a..50ddb147462e5ffbfeadae78035af51b24ca9997 100644 (file)
--- a/test/CodeGen/R600/llvm.sin.ll
+++ b/test/CodeGen/R600/llvm.sin.ll
@@ -21,7 +21,7 @@ define void @sin_f32(float addrspace(1)* %out, float %x) #1 {
 
 ; FUNC-LABEL: @sin_3x_f32
 ; SI-UNSAFE-NOT: V_ADD_F32
-; SI-UNSAFE: 4.774648e-01
+; SI-UNSAFE: 0x3ef47644
 ; SI-UNSAFE: V_MUL_F32
 ; SI-SAFE: V_MUL_F32
 ; SI-SAFE: V_MUL_F32
@@ -37,7 +37,7 @@ define void @sin_3x_f32(float addrspace(1)* %out, float %x) #1 {
 
 ; FUNC-LABEL: @sin_2x_f32
 ; SI-UNSAFE-NOT: V_ADD_F32
-; SI-UNSAFE: 3.183099e-01
+; SI-UNSAFE: 0x3ea2f983
 ; SI-UNSAFE: V_MUL_F32
 ; SI-SAFE: V_ADD_F32
 ; SI-SAFE: V_MUL_F32
@@ -52,7 +52,7 @@ define void @sin_2x_f32(float addrspace(1)* %out, float %x) #1 {
 }
 
 ; FUNC-LABEL: @test_2sin_f32
-; SI-UNSAFE: 3.183099e-01
+; SI-UNSAFE: 0x3ea2f983
 ; SI-UNSAFE: V_MUL_F32
 ; SI-SAFE: V_ADD_F32
 ; SI-SAFE: V_MUL_F32

diff --git a/test/CodeGen/R600/uint_to_fp.ll b/test/CodeGen/R600/uint_to_fp.ll
index 8f5d42d42c6b5f65754bc19591bcf643c3e63f64..9d4dacff3710a25fcd24f7179ef29270569b00c6 100644 (file)
--- a/test/CodeGen/R600/uint_to_fp.ll
+++ b/test/CodeGen/R600/uint_to_fp.ll
@@ -49,7 +49,7 @@ entry:
 
 ; FUNC-LABEL: @uint_to_fp_i1_f32:
 ; SI: V_CMP_EQ_I32_e64 [[CMP:s\[[0-9]+:[0-9]\]]],
-; SI-NEXT: V_CNDMASK_B32_e64 [[RESULT:v[0-9]+]], 0, 1.000000e+00, [[CMP]]
+; SI-NEXT: V_CNDMASK_B32_e64 [[RESULT:v[0-9]+]], 0, 1.0, [[CMP]]
 ; SI: BUFFER_STORE_DWORD [[RESULT]],
 ; SI: S_ENDPGM
 define void @uint_to_fp_i1_f32(float addrspace(1)* %out, i32 %in) {
@@ -60,7 +60,7 @@ define void @uint_to_fp_i1_f32(float addrspace(1)* %out, i32 %in) {
 }
 
 ; FUNC-LABEL: @uint_to_fp_i1_f32_load:
-; SI: V_CNDMASK_B32_e64 [[RESULT:v[0-9]+]], 0, 1.000000e+00
+; SI: V_CNDMASK_B32_e64 [[RESULT:v[0-9]+]], 0, 1.0
 ; SI: BUFFER_STORE_DWORD [[RESULT]],
 ; SI: S_ENDPGM
 define void @uint_to_fp_i1_f32_load(float addrspace(1)* %out, i1 %in) {