Silence sign-compare warning and reduce nesting.

No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195932 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AArch64/AArch64ISelLowering.cpp b/lib/Target/AArch64/AArch64ISelLowering.cpp
index 15232523fe41201cb1e21f73e206d38c9aeb0cba..6ea4b483eb4c4fc831dce146f0d9909f47211d4f 100644 (file)
--- a/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -4239,13 +4239,13 @@ AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
                          DAG.getConstant(Lane + ExtLane, MVT::i64));
     }
     // Test if V1 is a CONCAT_VECTORS.
-    if (V1.getOpcode() == ISD::CONCAT_VECTORS) {
-      if (V1.getOperand(1).getOpcode() == ISD::UNDEF) {
-        assert((Lane < V1.getOperand(0).getValueType().getVectorNumElements())
-               && "Invalid vector lane access");
-        return DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, VT, V1.getOperand(0),
-                           DAG.getConstant(Lane, MVT::i64));
-      }
+    if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
+        V1.getOperand(1).getOpcode() == ISD::UNDEF) {
+      SDValue Op0 = V1.getOperand(0);
+      assert((unsigned)Lane < Op0.getValueType().getVectorNumElements() &&
+             "Invalid vector lane access");
+      return DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, VT, Op0,
+                         DAG.getConstant(Lane, MVT::i64));
     }
 
     return DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, VT, V1,