Minor code reorganization.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55071 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp
index 7cb888ccb9830838d83b57f5c278229495ea1118..954de1d059a3a026bf9aa044297fba9853bcef0e 100644 (file)
--- a/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -146,8 +146,8 @@ unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, ISD::NodeType,
 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
                                  const TargetRegisterClass* RC) {
   MachineRegisterInfo &MRI = MF->getRegInfo();
-  const TargetInstrDesc &II = TII->get(MachineInstOpcode);
   unsigned ResultReg = MRI.createVirtualRegister(RC);
+  const TargetInstrDesc &II = TII->get(MachineInstOpcode);
 
   MachineInstr *MI = BuildMI(*MF, II, ResultReg);
 
@@ -159,8 +159,8 @@ unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
                                   const TargetRegisterClass *RC,
                                   unsigned Op0) {
   MachineRegisterInfo &MRI = MF->getRegInfo();
-  const TargetInstrDesc &II = TII->get(MachineInstOpcode);
   unsigned ResultReg = MRI.createVirtualRegister(RC);
+  const TargetInstrDesc &II = TII->get(MachineInstOpcode);
 
   MachineInstr *MI = BuildMI(*MF, II, ResultReg);
   MI->addOperand(MachineOperand::CreateReg(Op0, false));
@@ -173,8 +173,8 @@ unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
                                    const TargetRegisterClass *RC,
                                    unsigned Op0, unsigned Op1) {
   MachineRegisterInfo &MRI = MF->getRegInfo();
-  const TargetInstrDesc &II = TII->get(MachineInstOpcode);
   unsigned ResultReg = MRI.createVirtualRegister(RC);
+  const TargetInstrDesc &II = TII->get(MachineInstOpcode);
 
   MachineInstr *MI = BuildMI(*MF, II, ResultReg);
   MI->addOperand(MachineOperand::CreateReg(Op0, false));