Make sure we're only storing a single bit here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118126 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp
index d89050e370b3238f3df73398ac1df3c4715478e8..d46ed95b1af8776917ce137a9fa6080f608679d4 100644 (file)
--- a/lib/Target/ARM/ARMFastISel.cpp
+++ b/lib/Target/ARM/ARMFastISel.cpp
@@ -811,7 +811,15 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg,
   bool needReg0Op = false;
   switch (VT.getSimpleVT().SimpleTy) {
     default: return false;
-    case MVT::i1:
+    case MVT::i1: {
+      unsigned Res = createResultReg(isThumb ? ARM::tGPRRegisterClass :
+                                               ARM::GPRRegisterClass);
+      unsigned Opc = isThumb ? ARM::t2ANDri : ARM::ANDri;
+      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
+                              TII.get(Opc), Res)
+                      .addReg(SrcReg).addImm(1));
+      SrcReg = Res;
+    } // Fallthrough here.
     case MVT::i8:
       StrOpc = isThumb ? ARM::t2STRBi12 : ARM::STRBi12;
       break;
@@ -841,7 +849,6 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg,
   if (isFloat)
     Offset /= 4;
 
-
   // FIXME: The 'needReg0Op' bit goes away once STRH is converted to
   // not use the mega-addrmode stuff.
   if (!needReg0Op)