MIPS: Move Cavium CP0 hwrena impl bits to cpu-feature-overrides.h
authorDavid Daney <ddaney@caviumnetworks.com>
Wed, 13 May 2009 22:59:56 +0000 (15:59 -0700)
committerRalf Baechle <ralf@linux-mips.org>
Wed, 17 Jun 2009 10:06:31 +0000 (11:06 +0100)
We had an ugly #ifdef for Cavium Octeon hwrena bits in traps.c, remove
it to mach-cavium-octeon/cpu-feature-overrides.h

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
arch/mips/kernel/traps.c

index bb291f41b6a3e06bc48b63c1df7a2b913d6d7ae2..3d830756b13a4cf7b11fd5f51cb1c116e01675e3 100644 (file)
@@ -53,6 +53,7 @@
 #define cpu_has_userlocal      0
 #define cpu_has_vint           0
 #define cpu_has_veic           0
+#define cpu_hwrena_impl_bits   0xc0000000
 #define ARCH_HAS_READ_CURRENT_TIMER 1
 #define ARCH_HAS_IRQ_PER_CPU   1
 #define ARCH_HAS_SPINLOCK_PREFETCH 1
index f54871797ab9cceb6d600e121be18dd06032a665..08f1edf355e80c51362e4e35822e4a109a419acc 100644 (file)
@@ -1510,10 +1510,6 @@ void __cpuinit per_cpu_trap_init(void)
                write_c0_hwrena(enable);
        }
 
-#ifdef CONFIG_CPU_CAVIUM_OCTEON
-       write_c0_hwrena(0xc000000f); /* Octeon has register 30 and 31 */
-#endif
-
 #ifdef CONFIG_MIPS_MT_SMTC
        if (!secondaryTC) {
 #endif /* CONFIG_MIPS_MT_SMTC */