Get the register and count from the register list operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118458 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMMCCodeEmitter.cpp b/lib/Target/ARM/ARMMCCodeEmitter.cpp
index 296a5c9ce3646d4a8ba6e2058ca7d344a79e69c9..fe6bd34a2b600ba0fa01b35031b1754a9a5e9521 100644 (file)
--- a/lib/Target/ARM/ARMMCCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMMCCodeEmitter.cpp
@@ -378,14 +378,11 @@ getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
 
 unsigned ARMMCCodeEmitter::
 getRegisterListOpValue(const MCInst &MI, unsigned Op,
-                       SmallVectorImpl<MCFixup> &Fixups) const {
-  // Convert a list of GPRs into a bitfield (R0 -> bit 0). For each
-  // register in the list, set the corresponding bit.
-  unsigned Binary = 0;
-  for (unsigned i = Op, e = MI.getNumOperands(); i < e; ++i) {
-    unsigned regno = getARMRegisterNumbering(MI.getOperand(i).getReg());
-    Binary |= 1 << regno;
-  }
+                       SmallVectorImpl<MCFixup> &) const {
+  // {12-8} = Rd
+  // {7-0}  = count
+  unsigned Binary = getARMRegisterNumbering(MI.getOperand(Op).getReg()) << 8;
+  Binary |= MI.getOperand(Op + 1).getImm() & 0xFF;
   return Binary;
 }