ARM disassembler did not react to recent changes to the NEON instruction table.

VLD1q*_UPD and VST1q*_UPD have the ${dst:dregpair} operand now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101784 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
index 0301643970b7b7c91321a054b03104f03bcdb487..6d2d60a0db85d19271f1f1f26ed79336fab43a74 100644 (file)
--- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
@@ -2232,6 +2232,22 @@ static unsigned decodeN3VImm(uint32_t insn) {
   return (insn >> 8) & 0xF;
 }
 
+static bool UseDRegPair(unsigned Opcode) {
+  switch (Opcode) {
+  default:
+    return false;
+  case ARM::VLD1q8_UPD:
+  case ARM::VLD1q16_UPD:
+  case ARM::VLD1q32_UPD:
+  case ARM::VLD1q64_UPD:
+  case ARM::VST1q8_UPD:
+  case ARM::VST1q16_UPD:
+  case ARM::VST1q32_UPD:
+  case ARM::VST1q64_UPD:
+    return true;
+  }
+}
+
 // VLD*
 //   D[d] D[d2] ... Rn [TIED_TO Rn] align [Rm]
 // VLD*LN*
@@ -2305,11 +2321,9 @@ static bool DisassembleNLdSt0(MCInst &MI, unsigned Opcode, uint32_t insn,
 
     RegClass = OpInfo[OpIdx].RegClass;
     while (OpIdx < NumOps && OpInfo[OpIdx].RegClass == RegClass) {
-      if (Opcode >= ARM::VST1q16 && Opcode <= ARM::VST1q8)
-        MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClass, Rd,
-                                                           true)));
-      else
-        MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClass,Rd)));
+      MI.addOperand(MCOperand::CreateReg(
+                      getRegisterEnum(B, RegClass, Rd,
+                                      UseDRegPair(Opcode))));
       Rd += Inc;
       ++OpIdx;
     }
@@ -2327,11 +2341,9 @@ static bool DisassembleNLdSt0(MCInst &MI, unsigned Opcode, uint32_t insn,
     RegClass = OpInfo[0].RegClass;
 
     while (OpIdx < NumOps && OpInfo[OpIdx].RegClass == RegClass) {
-      if (Opcode >= ARM::VLD1q16 && Opcode <= ARM::VLD1q8)
-        MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClass, Rd,
-                                                           true)));
-      else
-        MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClass, Rd)));
+      MI.addOperand(MCOperand::CreateReg(
+                      getRegisterEnum(B, RegClass, Rd,
+                                      UseDRegPair(Opcode))));
       Rd += Inc;
       ++OpIdx;
     }

diff --git a/test/MC/Disassembler/neon-tests.txt b/test/MC/Disassembler/neon-tests.txt
index 64b490909200d8b168f9f0a321ab85cc5c343abb..51b31e7c1a6e50a415d82b9042c16d4694743add 100644 (file)
--- a/test/MC/Disassembler/neon-tests.txt
+++ b/test/MC/Disassembler/neon-tests.txt
@@ -9,6 +9,10 @@
 # CHECK:       vdup.32 q3, d1[0]
 0x41 0x6c 0xb4 0xf3
 
+# VLD1q8_UPD (with ${dst:dregpair} operand)
+# CHECK:       vld1.8  {d17, d18}, [r6], r5
+0x05 0x1a 0x66 0xf4
+
 # CHECK:       vld4.8  {d0, d1, d2, d3}, [r2], r7
 0x07 0x00 0x22 0xf4