Revert "Don't check liveness of unallocatable registers."

The ARM target depends on CPSR liveness being tracked after register
allocation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136548 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/MachineVerifier.cpp b/lib/CodeGen/MachineVerifier.cpp
index f798c1346e0ea06063319f9bf7e4959bce7924a6..8541d18ef3efbc1de9c0e4d9761f0720ab81e9c2 100644 (file)
--- a/lib/CodeGen/MachineVerifier.cpp
+++ b/lib/CodeGen/MachineVerifier.cpp
@@ -664,15 +664,8 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
       // Use of a dead register.
       if (!regsLive.count(Reg)) {
         if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
-          // Reserved registers may be used even when 'dead', but allocatable
-          // registers can't.
-          // We track the liveness of unreserved, unallocatable registers while
-          // the machine function is still in SSA form. That lets us check for
-          // bad EFLAGS uses. After register allocation, the unallocatable
-          // registers are probably quite wrong. For example, the x87 ST0-ST7
-          // registers don't track liveness at all.
-          if (!isReserved(Reg) &&
-              (MRI->isSSA() || TRI->isInAllocatableClass(Reg)))
+          // Reserved registers may be used even when 'dead'.
+          if (!isReserved(Reg))
             report("Using an undefined physical register", MO, MONum);
         } else {
           BBInfo &MInfo = MBBInfoMap[MI->getParent()];

diff --git a/lib/CodeGen/RegisterScavenging.cpp b/lib/CodeGen/RegisterScavenging.cpp
index 4fc711e1b8bd82123488196a4e910d06c50acc0f..9e9a145b0aa45ec1459070b20a500a4715624fce 100644 (file)
--- a/lib/CodeGen/RegisterScavenging.cpp
+++ b/lib/CodeGen/RegisterScavenging.cpp
@@ -157,7 +157,7 @@ void RegScavenger::forward() {
     if (!MO.isReg())
       continue;
     unsigned Reg = MO.getReg();
-    if (!Reg || isReserved(Reg) || !TRI->isInAllocatableClass(Reg))
+    if (!Reg || isReserved(Reg))
       continue;
 
     if (MO.isUse()) {
@@ -184,7 +184,7 @@ void RegScavenger::forward() {
     if (!MO.isReg())
       continue;
     unsigned Reg = MO.getReg();
-    if (!Reg || isReserved(Reg) || !TRI->isInAllocatableClass(Reg))
+    if (!Reg || isReserved(Reg))
       continue;
     if (MO.isUse()) {
       if (MO.isUndef())

diff --git a/test/CodeGen/X86/vector.ll b/test/CodeGen/X86/vector.ll
index 4268d02c5a13a069dd733d59ddc3404063b2322f..46b0e1890f11a8da09b651017f22af07834923bb 100644 (file)
--- a/test/CodeGen/X86/vector.ll
+++ b/test/CodeGen/X86/vector.ll
@@ -1,6 +1,6 @@
 ; Test that vectors are scalarized/lowered correctly.
 ; RUN: llc < %s -march=x86 -mcpu=i386 > %t
-; RUN: llc < %s -march=x86 -mcpu=yonah -verify-machineinstrs >> %t
+; RUN: llc < %s -march=x86 -mcpu=yonah >> %t
 
 %d8 = type <8 x double>
 %f1 = type <1 x float>