Akira,

Hope you are feeling better.

The Mips RDHWR (Read Hardware Register) instruction was not
tested for assembler or dissassembler consumption. This patch
adds that functionality.

Contributer: Vladimir Medic

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172579 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 57338df53cb56ada7e2efe2f20fd315864634f20..482210673a5695899e16e453a32f6c6c4d63d3d4 100644 (file)
--- a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -1071,6 +1071,9 @@ MipsAsmParser::parseHWRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
 
 MipsAsmParser::OperandMatchResultTy
 MipsAsmParser::parseHW64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
+
+  if (!isMips64())
+    return MatchOperand_NoMatch;
     //if the first token is not '$' we have error
   if (Parser.getTok().isNot(AsmToken::Dollar))
     return MatchOperand_NoMatch;
@@ -1088,7 +1091,7 @@ MipsAsmParser::parseHW64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
 
   MipsOperand *op = MipsOperand::CreateReg(Mips::HWR29_64, S,
         Parser.getTok().getLoc());
-  op->setRegKind(MipsOperand::Kind_HWRegs);
+  op->setRegKind(MipsOperand::Kind_HW64Regs);
   Operands.push_back(op);
 
   Parser.Lex(); // Eat reg number

diff --git a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
index 1efeffd32816d81668a145f8429c20c730433ccc..9560f3fc52477e235fbb4a66d407e89a6a8b094f 100644 (file)
--- a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
+++ b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
@@ -128,6 +128,11 @@ static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
                                               uint64_t Address,
                                               const void *Decoder);
 
+static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst,
+                                                unsigned Insn,
+                                                uint64_t Address,
+                                                const void *Decoder);
+
 static DecodeStatus DecodeACRegsRegisterClass(MCInst &Inst,
                                               unsigned RegNo,
                                               uint64_t Address,
@@ -454,6 +459,17 @@ static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst,
+                                                unsigned RegNo,
+                                                uint64_t Address,
+                                                const void *Decoder) {
+  //Currently only hardware register 29 is supported
+  if (RegNo != 29)
+    return  MCDisassembler::Fail;
+  Inst.addOperand(MCOperand::CreateReg(Mips::HWR29_64));
+  return MCDisassembler::Success;
+}
+
 static DecodeStatus DecodeACRegsRegisterClass(MCInst &Inst,
                                               unsigned RegNo,
                                               uint64_t Address,

diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td
index c6eb0e1e87a4bb2a44f6eb1be87394c5ae1612b7..f93dd86c17629dd1b0447b778737d71620cd7400 100644 (file)
--- a/lib/Target/Mips/MipsRegisterInfo.td
+++ b/lib/Target/Mips/MipsRegisterInfo.td
@@ -373,6 +373,6 @@ def HWRegsOpnd : RegisterOperand<HWRegs, "printCPURegs"> {
   let ParserMatchClass = HWRegsAsmOperand;
 }
 
-def HW64RegsOpnd : RegisterOperand<HWRegs, "printCPURegs"> {
+def HW64RegsOpnd : RegisterOperand<HWRegs64, "printCPURegs"> {
   let ParserMatchClass = HW64RegsAsmOperand;
 }

diff --git a/test/MC/Disassembler/Mips/mips32.txt b/test/MC/Disassembler/Mips/mips32.txt
index a1933190b1412f575590bcbe35a0d9b9c5d22a78..70224860bc7107bebccf493f194c544c57db37d7 100644 (file)
--- a/test/MC/Disassembler/Mips/mips32.txt
+++ b/test/MC/Disassembler/Mips/mips32.txt
@@ -404,3 +404,9 @@
 
 # CHECK: xori  $9,  $6, 17767
 0x38 0xc9 0x45 0x67
+
+# CHECK: .set    push
+# CHECK: .set    mips32r2
+# CHECK: rdhwr   $5, $29
+# CHECK: .set    pop
+0x7c 0x05 0xe8 0x3b

diff --git a/test/MC/Disassembler/Mips/mips32_le.txt b/test/MC/Disassembler/Mips/mips32_le.txt
index 08b36726baf3e948a339faf6c07e43d236151a21..48fa8e2c7fac10ce4b8aa50b63768990a213b0de 100644 (file)
--- a/test/MC/Disassembler/Mips/mips32_le.txt
+++ b/test/MC/Disassembler/Mips/mips32_le.txt
@@ -404,3 +404,9 @@
 
 # CHECK: xori  $9,  $6, 17767
 0x67 0x45 0xc9 0x38
+
+# CHECK: .set    push
+# CHECK: .set    mips32r2
+# CHECK: rdhwr   $5, $29
+# CHECK: .set    pop
+0x3b 0xe8 0x05 0x7c

diff --git a/test/MC/Mips/mips-alu-instructions.s b/test/MC/Mips/mips-alu-instructions.s
index ee2a9a0db45f75e4ffc930f6ec45f39ede1247cf..52fd900091dc9b7b3d14a9d3e6f99e509336d593 100644 (file)
--- a/test/MC/Mips/mips-alu-instructions.s
+++ b/test/MC/Mips/mips-alu-instructions.s
@@ -81,6 +81,10 @@
 # CHECK:  sub     $6, $zero, $7  # encoding: [0x22,0x30,0x07,0x00]
 # CHECK:  subu    $6, $zero, $7  # encoding: [0x23,0x30,0x07,0x00]
 # CHECK:  addu    $7, $8, $zero  # encoding: [0x21,0x38,0x00,0x01]
+# CHECK:  .set    push
+# CHECK:  .set    mips32r2
+# CHECK:  rdhwr   $5, $29
+# CHECK:  .set    pop            # encoding: [0x3b,0xe8,0x05,0x7c]
     add    $9,$6,$7
     add    $9,$6,17767
     addu   $9,$6,-15001
@@ -98,3 +102,4 @@
     neg    $6,$7
     negu   $6,$7
     move   $7,$8
+    rdhwr   $5, $29

diff --git a/test/MC/Mips/mips64-alu-instructions.s b/test/MC/Mips/mips64-alu-instructions.s
index a77ed43ff10ce03ee68fa3e241ca6ea9f0e35b2c..d30ddeee71711411aeb343ad7321545966640644 100644 (file)
--- a/test/MC/Mips/mips64-alu-instructions.s
+++ b/test/MC/Mips/mips64-alu-instructions.s
@@ -78,6 +78,11 @@
 # CHECK:  multu  $3, $5          # encoding: [0x19,0x00,0x65,0x00]
 # CHECK:  dsubu   $4, $3, $5      # encoding: [0x2f,0x20,0x65,0x00]
 # CHECK:  daddu    $7, $8, $zero  # encoding: [0x2d,0x38,0x00,0x01]
+# CHECK:  .set    push                                            
+# CHECK:  .set    mips32r2                                        
+# CHECK:  rdhwr   $5, $29                                         
+# CHECK:  .set    pop            # encoding: [0x3b,0xe8,0x05,0x7c]
+
     dadd    $9,$6,$7
     dadd    $9,$6,17767
     daddu   $9,$6,-15001
@@ -92,3 +97,4 @@
     multu  $3,$5
     dsubu   $4,$3,$5
     move   $7,$8
+    rdhwr   $5, $29