[ARM64] Floating point to fixed point scaled conversions are only available on fcvtzs...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205878 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM64/ARM64InstrFormats.td b/lib/Target/ARM64/ARM64InstrFormats.td
index 00658edefa52bbdd356681ee3c1cc4f7b959fca8..f4ad842f242576acf649ebec988a24590494e1aa 100644 (file)
--- a/lib/Target/ARM64/ARM64InstrFormats.td
+++ b/lib/Target/ARM64/ARM64InstrFormats.td
@@ -3044,7 +3044,7 @@ class BaseFPToIntegerUnscaled<bits<2> type, bits<2> rmode, bits<3> opcode,
       Sched<[WriteFCvt]> {
   bits<5> Rd;
   bits<5> Rn;
-  let Inst{30}    = 0;
+  let Inst{30-29} = 0b00;
   let Inst{28-24} = 0b11110;
   let Inst{23-22} = type;
   let Inst{21}    = 1;
@@ -3076,7 +3076,8 @@ class BaseFPToInteger<bits<2> type, bits<2> rmode, bits<3> opcode,
   let Inst{4-0}   = Rd;
 }
 
-multiclass FPToInteger<bits<2> rmode, bits<3> opcode, string asm, SDPatternOperator OpN> {
+multiclass FPToIntegerUnscaled<bits<2> rmode, bits<3> opcode, string asm,
+           SDPatternOperator OpN> {
   // Unscaled single-precision to 32-bit
   def UWSr : BaseFPToIntegerUnscaled<0b00, rmode, opcode, FPR32, GPR32, asm,
                                      [(set GPR32:$Rd, (OpN FPR32:$Rn))]> {
@@ -3100,7 +3101,10 @@ multiclass FPToInteger<bits<2> rmode, bits<3> opcode, string asm, SDPatternOpera
                                      [(set GPR64:$Rd, (OpN (f64 FPR64:$Rn)))]> {
     let Inst{31} = 1; // 64-bit GPR flag
   }
+}
 
+multiclass FPToIntegerScaled<bits<2> rmode, bits<3> opcode, string asm,
+           SDPatternOperator OpN> {
   // Scaled single-precision to 32-bit
   def SWSri : BaseFPToInteger<0b00, rmode, opcode, FPR32, GPR32,
                               fixedpoint32, asm> {

diff --git a/lib/Target/ARM64/ARM64InstrInfo.td b/lib/Target/ARM64/ARM64InstrInfo.td
index 376d39e748217f5ee87cfd24e179ef8c0c96362a..35a73f923c88e975b43594e7b03b6ef0d53871de 100644 (file)
--- a/lib/Target/ARM64/ARM64InstrInfo.td
+++ b/lib/Target/ARM64/ARM64InstrInfo.td
@@ -1859,19 +1859,23 @@ def STXPX  : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">;
 // Scaled floating point to integer conversion instructions.
 //===----------------------------------------------------------------------===//
 
-defm FCVTAS : FPToInteger<0b00, 0b100, "fcvtas", int_arm64_neon_fcvtas>;
-defm FCVTAU : FPToInteger<0b00, 0b101, "fcvtau", int_arm64_neon_fcvtau>;
-defm FCVTMS : FPToInteger<0b10, 0b000, "fcvtms", int_arm64_neon_fcvtms>;
-defm FCVTMU : FPToInteger<0b10, 0b001, "fcvtmu", int_arm64_neon_fcvtmu>;
-defm FCVTNS : FPToInteger<0b00, 0b000, "fcvtns", int_arm64_neon_fcvtns>;
-defm FCVTNU : FPToInteger<0b00, 0b001, "fcvtnu", int_arm64_neon_fcvtnu>;
-defm FCVTPS : FPToInteger<0b01, 0b000, "fcvtps", int_arm64_neon_fcvtps>;
-defm FCVTPU : FPToInteger<0b01, 0b001, "fcvtpu", int_arm64_neon_fcvtpu>;
-defm FCVTZS : FPToInteger<0b11, 0b000, "fcvtzs", fp_to_sint>;
-defm FCVTZU : FPToInteger<0b11, 0b001, "fcvtzu", fp_to_uint>;
+defm FCVTAS : FPToIntegerUnscaled<0b00, 0b100, "fcvtas", int_arm64_neon_fcvtas>;
+defm FCVTAU : FPToIntegerUnscaled<0b00, 0b101, "fcvtau", int_arm64_neon_fcvtau>;
+defm FCVTMS : FPToIntegerUnscaled<0b10, 0b000, "fcvtms", int_arm64_neon_fcvtms>;
+defm FCVTMU : FPToIntegerUnscaled<0b10, 0b001, "fcvtmu", int_arm64_neon_fcvtmu>;
+defm FCVTNS : FPToIntegerUnscaled<0b00, 0b000, "fcvtns", int_arm64_neon_fcvtns>;
+defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_arm64_neon_fcvtnu>;
+defm FCVTPS : FPToIntegerUnscaled<0b01, 0b000, "fcvtps", int_arm64_neon_fcvtps>;
+defm FCVTPU : FPToIntegerUnscaled<0b01, 0b001, "fcvtpu", int_arm64_neon_fcvtpu>;
+defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
+defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
+defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
+defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
 let isCodeGenOnly = 1 in {
-defm FCVTZS_Int : FPToInteger<0b11, 0b000, "fcvtzs", int_arm64_neon_fcvtzs>;
-defm FCVTZU_Int : FPToInteger<0b11, 0b001, "fcvtzu", int_arm64_neon_fcvtzu>;
+defm FCVTZS_Int : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", int_arm64_neon_fcvtzs>;
+defm FCVTZU_Int : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", int_arm64_neon_fcvtzu>;
+defm FCVTZS_Int : FPToIntegerScaled<0b11, 0b000, "fcvtzs", int_arm64_neon_fcvtzs>;
+defm FCVTZU_Int : FPToIntegerScaled<0b11, 0b001, "fcvtzu", int_arm64_neon_fcvtzu>;
 }
 
 //===----------------------------------------------------------------------===//

diff --git a/test/MC/ARM64/fp-encoding.s b/test/MC/ARM64/fp-encoding.s
index 25474c115307545c48a845049b11a56d623fc956..a780ee38f1252a7fd825d889ea0ec7e7166dd3e9 100644 (file)
--- a/test/MC/ARM64/fp-encoding.s
+++ b/test/MC/ARM64/fp-encoding.s
@@ -158,148 +158,84 @@ foo:
 ; CHECK: fcvt h1, s2                 ; encoding: [0x41,0xc0,0x23,0x1e]
 
   fcvtas w1, d2
-  fcvtas w1, d2, #1
   fcvtas x1, d2
-  fcvtas x1, d2, #1
   fcvtas w1, s2
-  fcvtas w1, s2, #1
   fcvtas x1, s2
-  fcvtas x1, s2, #1
 
 ; CHECK: fcvtas        w1, d2                  ; encoding: [0x41,0x00,0x64,0x1e]
-; CHECK: fcvtas        w1, d2, #1              ; encoding: [0x41,0xfc,0x44,0x1e]
 ; CHECK: fcvtas        x1, d2                  ; encoding: [0x41,0x00,0x64,0x9e]
-; CHECK: fcvtas        x1, d2, #1              ; encoding: [0x41,0xfc,0x44,0x9e]
 ; CHECK: fcvtas        w1, s2                  ; encoding: [0x41,0x00,0x24,0x1e]
-; CHECK: fcvtas        w1, s2, #1              ; encoding: [0x41,0xfc,0x04,0x1e]
 ; CHECK: fcvtas        x1, s2                  ; encoding: [0x41,0x00,0x24,0x9e]
-; CHECK: fcvtas        x1, s2, #1              ; encoding: [0x41,0xfc,0x04,0x9e]
 
   fcvtau w1, s2
-  fcvtau w1, s2, #1
   fcvtau w1, d2
-  fcvtau w1, d2, #1
   fcvtau x1, s2
-  fcvtau x1, s2, #1
   fcvtau x1, d2
-  fcvtau x1, d2, #1
 
 ; CHECK: fcvtau        w1, s2                  ; encoding: [0x41,0x00,0x25,0x1e]
-; CHECK: fcvtau        w1, s2, #1              ; encoding: [0x41,0xfc,0x05,0x1e]
 ; CHECK: fcvtau        w1, d2                  ; encoding: [0x41,0x00,0x65,0x1e]
-; CHECK: fcvtau        w1, d2, #1              ; encoding: [0x41,0xfc,0x45,0x1e]
 ; CHECK: fcvtau        x1, s2                  ; encoding: [0x41,0x00,0x25,0x9e]
-; CHECK: fcvtau        x1, s2, #1              ; encoding: [0x41,0xfc,0x05,0x9e]
 ; CHECK: fcvtau        x1, d2                  ; encoding: [0x41,0x00,0x65,0x9e]
-; CHECK: fcvtau        x1, d2, #1              ; encoding: [0x41,0xfc,0x45,0x9e]
 
   fcvtms w1, s2
-  fcvtms w1, s2, #1
   fcvtms w1, d2
-  fcvtms w1, d2, #1
   fcvtms x1, s2
-  fcvtms x1, s2, #1
   fcvtms x1, d2
-  fcvtms x1, d2, #1
 
 ; CHECK: fcvtms        w1, s2                  ; encoding: [0x41,0x00,0x30,0x1e]
-; CHECK: fcvtms        w1, s2, #1              ; encoding: [0x41,0xfc,0x10,0x1e]
 ; CHECK: fcvtms        w1, d2                  ; encoding: [0x41,0x00,0x70,0x1e]
-; CHECK: fcvtms        w1, d2, #1              ; encoding: [0x41,0xfc,0x50,0x1e]
 ; CHECK: fcvtms        x1, s2                  ; encoding: [0x41,0x00,0x30,0x9e]
-; CHECK: fcvtms        x1, s2, #1              ; encoding: [0x41,0xfc,0x10,0x9e]
 ; CHECK: fcvtms        x1, d2                  ; encoding: [0x41,0x00,0x70,0x9e]
-; CHECK: fcvtms        x1, d2, #1              ; encoding: [0x41,0xfc,0x50,0x9e]
 
   fcvtmu w1, s2
-  fcvtmu w1, s2, #1
   fcvtmu w1, d2
-  fcvtmu w1, d2, #1
   fcvtmu x1, s2
-  fcvtmu x1, s2, #1
   fcvtmu x1, d2
-  fcvtmu x1, d2, #1
 
 ; CHECK: fcvtmu        w1, s2                  ; encoding: [0x41,0x00,0x31,0x1e]
-; CHECK: fcvtmu        w1, s2, #1              ; encoding: [0x41,0xfc,0x11,0x1e]
 ; CHECK: fcvtmu        w1, d2                  ; encoding: [0x41,0x00,0x71,0x1e]
-; CHECK: fcvtmu        w1, d2, #1              ; encoding: [0x41,0xfc,0x51,0x1e]
 ; CHECK: fcvtmu        x1, s2                  ; encoding: [0x41,0x00,0x31,0x9e]
-; CHECK: fcvtmu        x1, s2, #1              ; encoding: [0x41,0xfc,0x11,0x9e]
 ; CHECK: fcvtmu        x1, d2                  ; encoding: [0x41,0x00,0x71,0x9e]
-; CHECK: fcvtmu        x1, d2, #1              ; encoding: [0x41,0xfc,0x51,0x9e]
 
   fcvtns w1, s2
-  fcvtns w1, s2, #1
   fcvtns w1, d2
-  fcvtns w1, d2, #1
   fcvtns x1, s2
-  fcvtns x1, s2, #1
   fcvtns x1, d2
-  fcvtns x1, d2, #1
 
 ; CHECK: fcvtns        w1, s2                  ; encoding: [0x41,0x00,0x20,0x1e]
-; CHECK: fcvtns        w1, s2, #1              ; encoding: [0x41,0xfc,0x00,0x1e]
 ; CHECK: fcvtns        w1, d2                  ; encoding: [0x41,0x00,0x60,0x1e]
-; CHECK: fcvtns        w1, d2, #1              ; encoding: [0x41,0xfc,0x40,0x1e]
 ; CHECK: fcvtns        x1, s2                  ; encoding: [0x41,0x00,0x20,0x9e]
-; CHECK: fcvtns        x1, s2, #1              ; encoding: [0x41,0xfc,0x00,0x9e]
 ; CHECK: fcvtns        x1, d2                  ; encoding: [0x41,0x00,0x60,0x9e]
-; CHECK: fcvtns        x1, d2, #1              ; encoding: [0x41,0xfc,0x40,0x9e]
 
   fcvtnu w1, s2
-  fcvtnu w1, s2, #1
   fcvtnu w1, d2
-  fcvtnu w1, d2, #1
   fcvtnu x1, s2
-  fcvtnu x1, s2, #1
   fcvtnu x1, d2
-  fcvtnu x1, d2, #1
 
 ; CHECK: fcvtnu        w1, s2                  ; encoding: [0x41,0x00,0x21,0x1e]
-; CHECK: fcvtnu        w1, s2, #1              ; encoding: [0x41,0xfc,0x01,0x1e]
 ; CHECK: fcvtnu        w1, d2                  ; encoding: [0x41,0x00,0x61,0x1e]
-; CHECK: fcvtnu        w1, d2, #1              ; encoding: [0x41,0xfc,0x41,0x1e]
 ; CHECK: fcvtnu        x1, s2                  ; encoding: [0x41,0x00,0x21,0x9e]
-; CHECK: fcvtnu        x1, s2, #1              ; encoding: [0x41,0xfc,0x01,0x9e]
 ; CHECK: fcvtnu        x1, d2                  ; encoding: [0x41,0x00,0x61,0x9e]
-; CHECK: fcvtnu        x1, d2, #1              ; encoding: [0x41,0xfc,0x41,0x9e]
 
   fcvtps w1, s2
-  fcvtps w1, s2, #1
   fcvtps w1, d2
-  fcvtps w1, d2, #1
   fcvtps x1, s2
-  fcvtps x1, s2, #1
   fcvtps x1, d2
-  fcvtps x1, d2, #1
 
 ; CHECK: fcvtps        w1, s2                  ; encoding: [0x41,0x00,0x28,0x1e]
-; CHECK: fcvtps        w1, s2, #1              ; encoding: [0x41,0xfc,0x08,0x1e]
 ; CHECK: fcvtps        w1, d2                  ; encoding: [0x41,0x00,0x68,0x1e]
-; CHECK: fcvtps        w1, d2, #1              ; encoding: [0x41,0xfc,0x48,0x1e]
 ; CHECK: fcvtps        x1, s2                  ; encoding: [0x41,0x00,0x28,0x9e]
-; CHECK: fcvtps        x1, s2, #1              ; encoding: [0x41,0xfc,0x08,0x9e]
 ; CHECK: fcvtps        x1, d2                  ; encoding: [0x41,0x00,0x68,0x9e]
-; CHECK: fcvtps        x1, d2, #1              ; encoding: [0x41,0xfc,0x48,0x9e]
 
   fcvtpu w1, s2
-  fcvtpu w1, s2, #1
   fcvtpu w1, d2
-  fcvtpu w1, d2, #1
   fcvtpu x1, s2
-  fcvtpu x1, s2, #1
   fcvtpu x1, d2
-  fcvtpu x1, d2, #1
 
 ; CHECK: fcvtpu        w1, s2                  ; encoding: [0x41,0x00,0x29,0x1e]
-; CHECK: fcvtpu        w1, s2, #1              ; encoding: [0x41,0xfc,0x09,0x1e]
 ; CHECK: fcvtpu        w1, d2                  ; encoding: [0x41,0x00,0x69,0x1e]
-; CHECK: fcvtpu        w1, d2, #1              ; encoding: [0x41,0xfc,0x49,0x1e]
 ; CHECK: fcvtpu        x1, s2                  ; encoding: [0x41,0x00,0x29,0x9e]
-; CHECK: fcvtpu        x1, s2, #1              ; encoding: [0x41,0xfc,0x09,0x9e]
 ; CHECK: fcvtpu        x1, d2                  ; encoding: [0x41,0x00,0x69,0x9e]
-; CHECK: fcvtpu        x1, d2, #1              ; encoding: [0x41,0xfc,0x49,0x9e]
 
   fcvtzs w1, s2
   fcvtzs w1, s2, #1