drm/i915: use proper FBC base register on all new platforms

Starting from GEN5 the FBC base register is the same on all platforms.
GEN>=5 is the same condition as HAS_PCH_SPLIT except on BXT, so make
things work on BXT as well.

Motivated by Rodrigo's request to check FBC support on BXT.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Antti Koskipää <antti.koskipaa@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
index f8da71682c965758985192d861a3e09b0b5157ab..348ed5abcdbf6d9745193254952da8f85a8c6909 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -209,7 +209,7 @@ static int i915_setup_compression(struct drm_device *dev, int size, int fb_cpp)
 
        dev_priv->fbc.threshold = ret;
 
-       if (HAS_PCH_SPLIT(dev))
+       if (INTEL_INFO(dev_priv)->gen >= 5)
                I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start);
        else if (IS_GM45(dev)) {
                I915_WRITE(DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start);