ARM64: dts: rockchip: rk3366: assign parent for gpu and wifi.

Gpu's 480MHz need to select usbphy_480m as parent.
The jitter will be lower, if sclk_wifidsp is supplied by pll_wifi.

Change-Id: I13e5077d55ab80e5224bac36b469e39d556bd347
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

diff --git a/arch/arm64/boot/dts/rockchip/rk3366-tb.dts b/arch/arm64/boot/dts/rockchip/rk3366-tb.dts
index 943303b06855d2ac6b65bb589b95b15b46336fa5..8365d233d085c4e81f81bd78c872396a402bdda8 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3366-tb.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3366-tb.dts
@@ -814,6 +814,8 @@
        reset-names = "otg_ahb", "otg_phy", "otg_controller";
        /* 0 - Normal, 1 - Force Host, 2 - Force Device */
        rockchip,usb-mode = <0>;
+       assigned-clocks = <&cru SCLK_USBPHY480M>;
+       assigned-clock-parents = <&usbphy0>;
        status = "okay";
 };
 

diff --git a/arch/arm64/boot/dts/rockchip/rk3366.dtsi b/arch/arm64/boot/dts/rockchip/rk3366.dtsi
index 6b8096cccbd37589552f9159f59ea6c2c90fbe9d..75784150d756140cf5d005cca90460fa61395019 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3366.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3366.dtsi
@@ -683,7 +683,7 @@
                #clock-cells = <1>;
                #reset-cells = <1>;
                assigned-clocks =
-                       <&cru SCLK_32K>,
+                       <&cru SCLK_WIFIDSP>, <&cru SCLK_32K>,
                        <&cru DCLK_VOP_FULL>, <&cru DCLK_VOP_LITE>,
                        <&cru PLL_CPLL>, <&cru PLL_GPLL>,
                        <&cru PLL_NPLL>, <&cru PLL_MPLL>,
@@ -693,7 +693,7 @@
                        <&cru ACLK_BUS>, <&cru ACLK_PERI0>,
                        <&cru ACLK_PERI1>;
                assigned-clock-rates =
-                       <0>,
+                       <0>, <0>,
                        <0>, <0>,
                        <750000000>, <576000000>,
                        <594000000>, <594000000>,
@@ -703,7 +703,7 @@
                        <288000000>, <288000000>,
                        <144000000>;
                assigned-clock-parents =
-                       <&cru SCLK_32K_INTR>,
+                       <&cru SCLK_WIFI_WPLL>, <&cru SCLK_32K_INTR>,
                        <&cru SCLK_MPLL_SRC>, <&cru PLL_NPLL>;
        };