Reg_cache variable is used to lock step enable register
from being accessed and written by both TSC and ADC
at the same time.
However, it isn't updated anywhere in the code at all.
If both TSC and ADC are used, eventually 1FFFF is always
written enabling all 16 steps uselessly causing a mess.
Patch fixes it by correcting the locks and updates the
variable by reading the step enable register
Signed-off-by: Zubair Lutfullah <zubair.lutfullah@gmail.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
void am335x_tsc_se_set(struct ti_tscadc_dev *tsadc, u32 val)
{
spin_lock(&tsadc->reg_lock);
+ tsadc->reg_se_cache = tscadc_readl(tsadc, REG_SE);
tsadc->reg_se_cache |= val;
- spin_unlock(&tsadc->reg_lock);
-
am335x_tsc_se_update(tsadc);
+ spin_unlock(&tsadc->reg_lock);
}
EXPORT_SYMBOL_GPL(am335x_tsc_se_set);