video: tegra: correct typeo in HDMI parent clock setup

Change-Id: I7d1d1e8f0e627bc0b2d225af7dde29becc53f991
Signed-off-by: Erik Gilling <konkers@android.com>

diff --git a/drivers/video/tegra/dc/dc.c b/drivers/video/tegra/dc/dc.c
index 6331b30be38dbf02a460ee7130fbc1c79a8364b6..666e14cc9c22df7a5a35f937d15ae69230419edb 100644 (file)
--- a/drivers/video/tegra/dc/dc.c
+++ b/drivers/video/tegra/dc/dc.c
@@ -494,13 +494,13 @@ void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk)
                struct clk *pll_d_clk =
                        clk_get_sys(NULL, "pll_d");
 
-               if (dc->mode.pclk > 70000)
+               if (dc->mode.pclk > 70000000)
                        rate = 594000000;
                else
                        rate = 216000000;
 
                if (rate != clk_get_rate(pll_d_clk))
-                   clk_set_rate(pll_d_clk, rate);
+                       clk_set_rate(pll_d_clk, rate);
 
                if (clk_get_parent(clk) != pll_d_out0_clk)
                        clk_set_parent(clk, pll_d_out0_clk);