Add all the rest of the ADD and SUB variants, some of which are important for

64-bit support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18087 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td
index 02a1b1ef63c99852209702bc1b9c15ebded573d3..84d63e692d3b5368c82250b7e82270d767b9d1bf 100644 (file)
--- a/lib/Target/Sparc/SparcInstrInfo.td
+++ b/lib/Target/Sparc/SparcInstrInfo.td
@@ -116,13 +116,24 @@ def SRArr : F3_1<2, 0b100111, "sra">;
 def SRAri : F3_2<2, 0b100111, "sra">;
 
 // Section B.13 - Add Instructions, p. 108
-def ADDrr : F3_1<2, 0b000000, "add">;
-def ADDri : F3_2<2, 0b000000, "add">;
+def ADDrr   : F3_1<2, 0b000000, "add">;
+def ADDri   : F3_2<2, 0b000000, "add">;
+def ADDCCrr : F3_1<2, 0b010000, "addcc">;
+def ADDCCri : F3_2<2, 0b010000, "addcc">;
+def ADDXrr  : F3_1<2, 0b001000, "addx">;
+def ADDXri  : F3_2<2, 0b001000, "addx">;
+def ADDXCCrr: F3_1<2, 0b011000, "addxcc">;
+def ADDXCCri: F3_2<2, 0b011000, "addxcc">;
 
 // Section B.15 - Subtract Instructions, p. 110
 def SUBrr   : F3_1<2, 0b000100, "sub">;
+def SUBri   : F3_2<2, 0b000100, "sub">;
 def SUBCCrr : F3_1<2, 0b010100, "subcc">;
 def SUBCCri : F3_2<2, 0b010100, "subcc">;
+def SUBXrr  : F3_1<2, 0b001100, "subx">;
+def SUBXri  : F3_2<2, 0b001100, "subx">;
+def SUBXCCrr: F3_1<2, 0b011100, "subxcc">;
+def SUBXCCri: F3_2<2, 0b011100, "subxcc">;
 
 // Section B.18 - Multiply Instructions, p. 113
 def UMULrr : F3_1<2, 0b001010, "umul">;

diff --git a/lib/Target/SparcV8/SparcV8InstrInfo.td b/lib/Target/SparcV8/SparcV8InstrInfo.td
index 02a1b1ef63c99852209702bc1b9c15ebded573d3..84d63e692d3b5368c82250b7e82270d767b9d1bf 100644 (file)
--- a/lib/Target/SparcV8/SparcV8InstrInfo.td
+++ b/lib/Target/SparcV8/SparcV8InstrInfo.td
@@ -116,13 +116,24 @@ def SRArr : F3_1<2, 0b100111, "sra">;
 def SRAri : F3_2<2, 0b100111, "sra">;
 
 // Section B.13 - Add Instructions, p. 108
-def ADDrr : F3_1<2, 0b000000, "add">;
-def ADDri : F3_2<2, 0b000000, "add">;
+def ADDrr   : F3_1<2, 0b000000, "add">;
+def ADDri   : F3_2<2, 0b000000, "add">;
+def ADDCCrr : F3_1<2, 0b010000, "addcc">;
+def ADDCCri : F3_2<2, 0b010000, "addcc">;
+def ADDXrr  : F3_1<2, 0b001000, "addx">;
+def ADDXri  : F3_2<2, 0b001000, "addx">;
+def ADDXCCrr: F3_1<2, 0b011000, "addxcc">;
+def ADDXCCri: F3_2<2, 0b011000, "addxcc">;
 
 // Section B.15 - Subtract Instructions, p. 110
 def SUBrr   : F3_1<2, 0b000100, "sub">;
+def SUBri   : F3_2<2, 0b000100, "sub">;
 def SUBCCrr : F3_1<2, 0b010100, "subcc">;
 def SUBCCri : F3_2<2, 0b010100, "subcc">;
+def SUBXrr  : F3_1<2, 0b001100, "subx">;
+def SUBXri  : F3_2<2, 0b001100, "subx">;
+def SUBXCCrr: F3_1<2, 0b011100, "subxcc">;
+def SUBXCCri: F3_2<2, 0b011100, "subxcc">;
 
 // Section B.18 - Multiply Instructions, p. 113
 def UMULrr : F3_1<2, 0b001010, "umul">;