[mips] Implement MipsTargetMachine::getInstrItineraryData().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186227 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Mips/MipsSubtarget.h b/lib/Target/Mips/MipsSubtarget.h
index ef7568a81383c2f08ebcd49b39290dcc09d5e698..bfb13bb48023c1a8df472c3722749b0acf532e45 100644 (file)
--- a/lib/Target/Mips/MipsSubtarget.h
+++ b/lib/Target/Mips/MipsSubtarget.h
@@ -194,6 +194,7 @@ public:
   bool hasBitCount()  const { return HasBitCount; }
   bool hasFPIdx()     const { return HasFPIdx; }
 
+  const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
   bool allowMixed16_32() const { return inMips16ModeDefault() |
                                         AllowMixed16_32;}
 

diff --git a/lib/Target/Mips/MipsTargetMachine.cpp b/lib/Target/Mips/MipsTargetMachine.cpp
index 9af2f1b201d973953f81a99238ec94fa316a4f08..ced6a096740a9ce27c4149a0cfb73aab7de7c726 100644 (file)
--- a/lib/Target/Mips/MipsTargetMachine.cpp
+++ b/lib/Target/Mips/MipsTargetMachine.cpp
@@ -70,8 +70,8 @@ MipsTargetMachine(const Target &T, StringRef TT,
                 "E-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32-S64")),
     InstrInfo(MipsInstrInfo::create(*this)),
     FrameLowering(MipsFrameLowering::create(*this, Subtarget)),
-    TLInfo(MipsTargetLowering::create(*this)),
-    TSInfo(*this), JITInfo() {
+    TLInfo(MipsTargetLowering::create(*this)), TSInfo(*this),
+    InstrItins(Subtarget.getInstrItineraryData()), JITInfo() {
   initAsmInfo();
 }
 

diff --git a/lib/Target/Mips/MipsTargetMachine.h b/lib/Target/Mips/MipsTargetMachine.h
index ee557084fbbff89ddd025dbe0c700d72b5de90e5..5a9a11d861c0739fee7b7b94788b70cb7b9e5f07 100644 (file)
--- a/lib/Target/Mips/MipsTargetMachine.h
+++ b/lib/Target/Mips/MipsTargetMachine.h
@@ -44,6 +44,7 @@ class MipsTargetMachine : public LLVMTargetMachine {
   OwningPtr<const MipsFrameLowering> FrameLoweringSE;
   OwningPtr<const MipsTargetLowering> TLInfoSE;
   MipsSelectionDAGInfo TSInfo;
+  const InstrItineraryData &InstrItins;
   MipsJITInfo JITInfo;
 
 public:
@@ -65,6 +66,11 @@ public:
   { return &Subtarget; }
   virtual const DataLayout *getDataLayout()    const
   { return &DL;}
+
+  virtual const InstrItineraryData *getInstrItineraryData() const {
+    return Subtarget.inMips16Mode() ? 0 : &InstrItins;
+  }
+
   virtual MipsJITInfo *getJITInfo()
   { return &JITInfo; }
 

diff --git a/test/CodeGen/Mips/cmov.ll b/test/CodeGen/Mips/cmov.ll
index 81925a4953ce4e03917af7caa782498f8f7a8beb..ce0ffc371715bdc6a43367992650081cf8bcebda 100644 (file)
--- a/test/CodeGen/Mips/cmov.ll
+++ b/test/CodeGen/Mips/cmov.ll
@@ -5,12 +5,12 @@
 @i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4
 @i3 = common global i32* null, align 4
 
-; O32:  lw $[[R0:[0-9]+]], %got(i3)
-; O32:  addiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got(i1) 
-; O32:  movn $[[R0]], $[[R1]], ${{[0-9]+}} 
-; N64:  ldr $[[R0:[0-9]+]] 
-; N64:  ld $[[R1:[0-9]+]], %got_disp(i1)
-; N64:  movn $[[R0]], $[[R1]], ${{[0-9]+}} 
+; O32-DAG:  lw $[[R0:[0-9]+]], %got(i3)
+; O32-DAG:  addiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got(i1) 
+; O32:      movn $[[R0]], $[[R1]], ${{[0-9]+}} 
+; N64-DAG:  ldr $[[R0:[0-9]+]] 
+; N64-DAG:  ld $[[R1:[0-9]+]], %got_disp(i1)
+; N64:      movn $[[R0]], $[[R1]], ${{[0-9]+}} 
 define i32* @cmov1(i32 %s) nounwind readonly {
 entry:
   %tobool = icmp ne i32 %s, 0

diff --git a/test/CodeGen/Mips/fcopysign-f32-f64.ll b/test/CodeGen/Mips/fcopysign-f32-f64.ll
index b36473d6f57ace4f5bdf3ec5545e8e99136429e5..9f88d0c956b1919f67032f845ed02be7ea82223d 100644 (file)
--- a/test/CodeGen/Mips/fcopysign-f32-f64.ll
+++ b/test/CodeGen/Mips/fcopysign-f32-f64.ll
@@ -7,14 +7,15 @@ declare float @copysignf(float, float) nounwind readnone
 
 define float @func2(float %d, double %f) nounwind readnone {
 entry:
-; 64: func2
-; 64: lui  $[[T0:[0-9]+]], 32767
-; 64: ori  $[[MSK0:[0-9]+]], $[[T0]], 65535
-; 64: and  $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
-; 64: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 63
-; 64: sll  $[[SLL:[0-9]+]], ${{[0-9]+}}, 31
-; 64: or   $[[OR:[0-9]+]], $[[AND0]], $[[SLL]]
-; 64: mtc1 $[[OR]], $f0
+; 64:     func2
+; 64-DAG: lui  $[[T0:[0-9]+]], 32767
+; 64-DAG: ori  $[[MSK0:[0-9]+]], $[[T0]], 65535
+; 64-DAG: and  $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
+; 64-DAG: dsrl $[[DSRL:[0-9]+]], ${{[0-9]+}}, 63
+; 64-DAG: sll  $[[SLL0:[0-9]+]], $[[DSRL]], 0
+; 64-DAG: sll  $[[SLL1:[0-9]+]], $[[SLL0]], 31
+; 64:     or   $[[OR:[0-9]+]], $[[AND0]], $[[SLL1]]
+; 64:     mtc1 $[[OR]], $f0
 
 ; 64R2: dext ${{[0-9]+}}, ${{[0-9]+}}, 63, 1
 ; 64R2: ins  $[[INS:[0-9]+]], ${{[0-9]+}}, 31, 1
@@ -29,14 +30,16 @@ entry:
 define double @func3(double %d, float %f) nounwind readnone {
 entry:
 
-; 64: daddiu $[[T0:[0-9]+]], $zero, 1
-; 64: dsll   $[[T1:[0-9]+]], $[[T0]], 63
-; 64: daddiu $[[MSK0:[0-9]+]], $[[T1]], -1
-; 64: and    $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
-; 64: srl    ${{[0-9]+}}, ${{[0-9]+}}, 31
-; 64: dsll   $[[DSLL:[0-9]+]], ${{[0-9]+}}, 63
-; 64: or     $[[OR:[0-9]+]], $[[AND0]], $[[DSLL]]
-; 64: dmtc1  $[[OR]], $f0
+; 64:     func3
+; 64-DAG: daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-DAG: dsll   $[[T1:[0-9]+]], $[[T0]], 63
+; 64-DAG: daddiu $[[MSK0:[0-9]+]], $[[T1]], -1
+; 64-DAG: and    $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
+; 64-DAG: srl    $[[SRL:[0-9]+]], ${{[0-9]+}}, 31
+; 64-DAG: sll    $[[SLL:[0-9]+]], $[[SRL]], 0
+; 64-DAG: dsll   $[[DSLL:[0-9]+]], $[[SLL]], 63
+; 64:     or     $[[OR:[0-9]+]], $[[AND0]], $[[DSLL]]
+; 64:     dmtc1  $[[OR]], $f0
 
 ; 64R2: ext   ${{[0-9]+}}, ${{[0-9]+}}, 31, 1
 ; 64R2: dins  $[[INS:[0-9]+]], ${{[0-9]+}}, 63, 1

diff --git a/test/CodeGen/Mips/i64arg.ll b/test/CodeGen/Mips/i64arg.ll
index 704014cba0107e5f0c2274b133a451eb09b1ae31..0b16424d94c276b6b3532caad4b1c20c138668e7 100644 (file)
--- a/test/CodeGen/Mips/i64arg.ll
+++ b/test/CodeGen/Mips/i64arg.ll
@@ -17,12 +17,12 @@ entry:
 ; CHECK: jalr $25
   tail call void @ff2(i64 %ll, double 3.000000e+00) nounwind
   %sub = add nsw i32 %i, -1
-; CHECK: lw $25, %call16(ff3)
-; CHECK: sw $[[R1]], 28($sp)
-; CHECK: sw $[[R0]], 24($sp)
-; CHECK: move $6, $[[R2]]
-; CHECK: move $7, $[[R3]]
-; CHECK: jalr $25
+; CHECK-DAG: lw $25, %call16(ff3)
+; CHECK-DAG: sw $[[R1]], 28($sp)
+; CHECK-DAG: sw $[[R0]], 24($sp)
+; CHECK-DAG: move $6, $[[R2]]
+; CHECK-DAG: move $7, $[[R3]]
+; CHECK:     jalr $25
   tail call void @ff3(i32 %i, i64 %ll, i32 %sub, i64 %ll1) nounwind
   ret void
 }

diff --git a/test/CodeGen/Mips/mips64-f128.ll b/test/CodeGen/Mips/mips64-f128.ll
index 5892cab4f8eaf38be5b29e960c70738597ce971d..ab0a3d6b50fa115d27135c3d5e299cf86e4897e5 100644 (file)
--- a/test/CodeGen/Mips/mips64-f128.ll
+++ b/test/CodeGen/Mips/mips64-f128.ll
@@ -231,13 +231,13 @@ entry:
   ret double %conv
 }
 
-; CHECK: libcall1_fabsl:
-; CHECK: ld      $[[R0:[0-9]+]], 8($[[R4:[0-9]+]])
-; CHECK: daddiu  $[[R1:[0-9]+]], $zero, 1
-; CHECK: dsll    $[[R2:[0-9]+]], $[[R1]], 63
-; CHECK: daddiu  $[[R3:[0-9]+]], $[[R2]], -1
-; CHECK: and     $4, $[[R0]], $[[R3]]
-; CHECK: ld      $2, 0($[[R4]])
+; CHECK:             libcall1_fabsl:
+; CHECK-DAG: ld      $[[R0:[0-9]+]], 8($[[R4:[0-9]+]])
+; CHECK-DAG: daddiu  $[[R1:[0-9]+]], $zero, 1
+; CHECK-DAG: dsll    $[[R2:[0-9]+]], $[[R1]], 63
+; CHECK-DAG: daddiu  $[[R3:[0-9]+]], $[[R2]], -1
+; CHECK-DAG: and     $4, $[[R0]], $[[R3]]
+; CHECK-DAG: ld      $2, 0($[[R4]])
 
 define fp128 @libcall1_fabsl() {
 entry:
@@ -403,18 +403,18 @@ entry:
 
 declare fp128 @llvm.powi.f128(fp128, i32) #3
 
-; CHECK: libcall2_copysignl:
-; CHECK: daddiu $[[R2:[0-9]+]], $zero, 1
-; CHECK: dsll   $[[R3:[0-9]+]], $[[R2]], 63
-; CHECK: ld     $[[R0:[0-9]+]], %got_disp(gld1)
-; CHECK: ld     $[[R1:[0-9]+]], 8($[[R0]])
-; CHECK: and    $[[R4:[0-9]+]], $[[R1]], $[[R3]]
-; CHECK: ld     $[[R5:[0-9]+]], %got_disp(gld0)
-; CHECK: ld     $[[R6:[0-9]+]], 8($[[R5]])
-; CHECK: daddiu $[[R7:[0-9]+]], $[[R3]], -1
-; CHECK: and    $[[R8:[0-9]+]], $[[R6]], $[[R7]]
-; CHECK: or     $4, $[[R8]], $[[R4]]
-; CHECK: ld     $2, 0($[[R5]])
+; CHECK:     libcall2_copysignl:
+; CHECK-DAG: daddiu $[[R2:[0-9]+]], $zero, 1
+; CHECK-DAG: dsll   $[[R3:[0-9]+]], $[[R2]], 63
+; CHECK-DAG: ld     $[[R0:[0-9]+]], %got_disp(gld1)
+; CHECK-DAG: ld     $[[R1:[0-9]+]], 8($[[R0]])
+; CHECK-DAG: and    $[[R4:[0-9]+]], $[[R1]], $[[R3]]
+; CHECK-DAG: ld     $[[R5:[0-9]+]], %got_disp(gld0)
+; CHECK-DAG: ld     $[[R6:[0-9]+]], 8($[[R5]])
+; CHECK-DAG: daddiu $[[R7:[0-9]+]], $[[R3]], -1
+; CHECK-DAG: and    $[[R8:[0-9]+]], $[[R6]], $[[R7]]
+; CHECK-DAG: or     $4, $[[R8]], $[[R4]]
+; CHECK-DAG: ld     $2, 0($[[R5]])
 
 define fp128 @libcall2_copysignl() {
 entry:

diff --git a/test/CodeGen/Mips/return-vector.ll b/test/CodeGen/Mips/return-vector.ll
index 739c43c68a55e427b71c85b49b5979557f9dc984..6bb9523ffb144cfd8b848de5be7676b08f0155ff 100644 (file)
--- a/test/CodeGen/Mips/return-vector.ll
+++ b/test/CodeGen/Mips/return-vector.ll
@@ -179,11 +179,11 @@ entry:
   ret <4 x float> %vecins4
 
 ; CHECK:        return_f4:
-; CHECK:        lwc1    $[[R0:[a-z0-9]+]], 16($sp)
-; CHECK:        swc1    $[[R0]], 12($4)
-; CHECK:        sw      $7, 8($4)
-; CHECK:        sw      $6, 4($4)
-; CHECK:        sw      $5, 0($4)
+; CHECK-DAG:    lwc1    $[[R0:[a-z0-9]+]], 16($sp)
+; CHECK-DAG:    swc1    $[[R0]], 12($4)
+; CHECK-DAG:    sw      $7, 8($4)
+; CHECK-DAG:    sw      $6, 4($4)
+; CHECK-DAG:    sw      $5, 0($4)
 }
 
 
@@ -195,11 +195,11 @@ entry:
   %vecins4 = insertelement <4 x double> %vecins3, double %d, i32 3
   ret <4 x double> %vecins4
 
-; CHECK:        return_d4:
-; CHECK:        sdc1    $[[R0:[a-z0-9]+]], 24($4)
-; CHECK:        sdc1    $[[R1:[a-z0-9]+]], 16($4)
-; CHECK:        sdc1    $[[R2:[a-z0-9]+]], 8($4)
-; CHECK:        sdc1    $[[R3:[a-z0-9]+]], 0($4)
+; CHECK:            return_d4:
+; CHECK-DAG:        sdc1    $[[R0:[a-z0-9]+]], 24($4)
+; CHECK-DAG:        sdc1    $[[R1:[a-z0-9]+]], 16($4)
+; CHECK-DAG:        sdc1    $[[R2:[a-z0-9]+]], 8($4)
+; CHECK-DAG:        sdc1    $[[R3:[a-z0-9]+]], 0($4)
 }
 
 

diff --git a/test/CodeGen/Mips/tls-alias.ll b/test/CodeGen/Mips/tls-alias.ll
index ce98cc8262239e464a4e060aa26f13b0054d3373..3c810542cca31daef7b108c0b47b589fa5158876 100644 (file)
--- a/test/CodeGen/Mips/tls-alias.ll
+++ b/test/CodeGen/Mips/tls-alias.ll
@@ -4,7 +4,7 @@
 @bar = hidden alias i32* @foo
 
 define i32* @zed() {
-; CHECK: __tls_get_addr
-; CHECK-NEXT: %tlsgd(bar)
+; CHECK-DAG: __tls_get_addr
+; CHECK-DAG: %tlsgd(bar)
        ret i32* @bar
 }

diff --git a/test/CodeGen/Mips/tls.ll b/test/CodeGen/Mips/tls.ll
index b86d25e5e5e83f12ec2c3693b5cc46cecb74371c..d83edfd9fa1f95dd6ff6c89147b0ce2181ab5ef9 100644 (file)
--- a/test/CodeGen/Mips/tls.ll
+++ b/test/CodeGen/Mips/tls.ll
@@ -13,14 +13,14 @@ entry:
   %tmp = load i32* @t1, align 4
   ret i32 %tmp
 
-; CHECK: f1:
-
-; PIC:   addu    $[[R0:[a-z0-9]+]], $2, $25
-; PIC:   lw      $25, %call16(__tls_get_addr)($[[R0]])
-; PIC:   addiu   $4, $[[R0]], %tlsgd(t1)
-; PIC:   jalr    $25
-; PIC:   lw      $2, 0($2)
-
+; PIC:       f1:
+; PIC-DAG:   addu    $[[R0:[a-z0-9]+]], $2, $25
+; PIC-DAG:   lw      $25, %call16(__tls_get_addr)($[[R0]])
+; PIC-DAG:   addiu   $4, $[[R0]], %tlsgd(t1)
+; PIC-DAG:   jalr    $25
+; PIC-DAG:   lw      $2, 0($2)
+
+; STATIC:   f1:
 ; STATIC:   lui     $[[R0:[0-9]+]], %tprel_hi(t1)
 ; STATIC:   addiu   $[[R1:[0-9]+]], $[[R0]], %tprel_lo(t1)
 ; STATIC:   rdhwr   $3, $29
@@ -36,17 +36,19 @@ entry:
   %tmp = load i32* @t2, align 4
   ret i32 %tmp
 
-; CHECK: f2:
-
-; PIC:   addu    $[[R0:[a-z0-9]+]], $2, $25
-; PIC:   lw      $25, %call16(__tls_get_addr)($[[R0]])
-; PIC:   addiu   $4, $[[R0]], %tlsgd(t2)
-; PIC:   jalr    $25
-; PIC:   lw      $2, 0($2)
+; PIC:       f2:
+; PIC-DAG:   addu    $[[R0:[a-z0-9]+]], $2, $25
+; PIC-DAG:   lw      $25, %call16(__tls_get_addr)($[[R0]])
+; PIC-DAG:   addiu   $4, $[[R0]], %tlsgd(t2)
+; PIC-DAG:   jalr    $25
+; PIC-DAG:   lw      $2, 0($2)
 
+; STATICGP: f2:
 ; STATICGP: lui     $[[R0:[0-9]+]], %hi(__gnu_local_gp)
 ; STATICGP: addiu   $[[GP:[0-9]+]], $[[R0]], %lo(__gnu_local_gp)
 ; STATICGP: lw      ${{[0-9]+}}, %gottprel(t2)($[[GP]])
+
+; STATIC:   f2:
 ; STATIC:   lui     $[[R0:[0-9]+]], %hi(__gnu_local_gp)
 ; STATIC:   addiu   $[[GP:[0-9]+]], $[[R0]], %lo(__gnu_local_gp)
 ; STATIC:   rdhwr   $3, $29

diff --git a/test/CodeGen/Mips/unalignedload.ll b/test/CodeGen/Mips/unalignedload.ll
index 7f880b6fe37991381edea57f85bed43863327c10..19f3af7f344a79f58bba04601df6161e86cbd8fc 100644 (file)
--- a/test/CodeGen/Mips/unalignedload.ll
+++ b/test/CodeGen/Mips/unalignedload.ll
@@ -9,17 +9,17 @@
 
 define void @foo1() nounwind {
 entry:
-; CHECK-EL: lbu ${{[0-9]+}}, 2($[[R0:[0-9]+]])
-; CHECK-EL: lbu ${{[0-9]+}}, 3($[[R0]])
-; CHECK-EL: jalr
-; CHECK-EL: lwl $[[R1:[0-9]+]], 3($[[R2:[0-9]+]])
-; CHECK-EL: lwr $[[R1]], 0($[[R2]])
+; CHECK-EL-DAG: lbu ${{[0-9]+}}, 2($[[R0:[0-9]+]])
+; CHECK-EL-DAG: lbu ${{[0-9]+}}, 3($[[R0]])
+; CHECK-EL:     jalr
+; CHECK-EL-DAG: lwl $[[R1:[0-9]+]], 3($[[R2:[0-9]+]])
+; CHECK-EL-DAG: lwr $[[R1]], 0($[[R2]])
 
-; CHECK-EB: lbu ${{[0-9]+}}, 3($[[R0:[0-9]+]])
-; CHECK-EB: lbu ${{[0-9]+}}, 2($[[R0]])
-; CHECK-EB: jalr
-; CHECK-EB: lwl $[[R1:[0-9]+]], 0($[[R2:[0-9]+]])
-; CHECK-BE: lwr $[[R1]], 3($[[R2]])
+; CHECK-EB-DAG: lbu ${{[0-9]+}}, 3($[[R0:[0-9]+]])
+; CHECK-EB-DAG: lbu ${{[0-9]+}}, 2($[[R0]])
+; CHECK-EB:     jalr
+; CHECK-EB-DAG: lwl $[[R1:[0-9]+]], 0($[[R2:[0-9]+]])
+; CHECK-EB-DAG: lwr $[[R1]], 3($[[R2]])
 
   tail call void @foo2(%struct.S1* byval getelementptr inbounds (%struct.S2* @s2, i32 0, i32 1)) nounwind
   tail call void @foo4(%struct.S4* byval @s4) nounwind