Switch BCC, MOVCCr, etc. to PredicateOperand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36948 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp
index 9454fb717f43b8b4af29cac2837c767e04efd255..0f0a5419dd68ec8883072619c7f911f32af66626 100644 (file)
--- a/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -101,7 +101,7 @@ namespace {
     void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNo);
     void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNo);
     void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNo);
-    void printCCOperand(const MachineInstr *MI, int opNum);
+    void printPredicateOperand(const MachineInstr *MI, int opNum);
     void printPCLabel(const MachineInstr *MI, int opNum);
     void printRegisterList(const MachineInstr *MI, int opNum);
     void printCPInstOperand(const MachineInstr *MI, int opNum,
@@ -613,7 +613,7 @@ void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
   O << "]";
 }
 
-void ARMAsmPrinter::printCCOperand(const MachineInstr *MI, int opNum) {
+void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int opNum) {
   int CC = (int)MI->getOperand(opNum).getImmedValue();
   O << ARMCondCodeToString((ARMCC::CondCodes)CC);
 }

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 21f058586a0d8d1257790a4c23656bbce6882c85..5441212b865129c647dfb1dfe65eefa66a219305 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -162,11 +162,6 @@ def sext_16_node : PatLeaf<(i32 GPR:$a), [{
 // Branch target.
 def brtarget : Operand<OtherVT>;
 
-// Operand for printing out a condition code.
-def CCOp : Operand<i32> {
-  let PrintMethod = "printCCOperand";
-}
-
 // A list of registers separated by comma. Used by load/store multiple.
 def reglist : Operand<i32> {
   let PrintMethod = "printRegisterList";
@@ -282,6 +277,16 @@ def addrmodepc : Operand<i32>,
   let MIOperandInfo = (ops GPR, i32imm);
 }
 
+// ARM branch / cmov condition code operand.
+def ccop : PredicateOperand<i32, (ops i32imm), (ops)> {
+  let PrintMethod = "printPredicateOperand";
+}
+
+// ARM Predicate operand. Default to 14 = always (AL).
+def pred : PredicateOperand<i32, (ops i32imm), (ops (i32 14))> {
+  let PrintMethod = "printPredicateOperand";
+}
+
 //===----------------------------------------------------------------------===//
 // ARM Instruction flags.  These need to match ARMInstrInfo.h.
 //
@@ -579,7 +584,7 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
 }
 
 let isBranch = 1, isTerminator = 1, noResults = 1, isBarrier = 1 in
-  def Bcc : AI<(ops brtarget:$dst, CCOp:$cc), "b$cc $dst",
+  def Bcc : AI<(ops brtarget:$dst, ccop:$cc), "b$cc $dst",
                 [(ARMbrcond bb:$dst, imm:$cc)]>;
 
 //===----------------------------------------------------------------------===//
@@ -1041,17 +1046,17 @@ def : ARMPat<(ARMcmpNZ GPR:$src, so_imm_neg:$imm),
 
 
 // Conditional moves
-def MOVCCr : AI<(ops GPR:$dst, GPR:$false, GPR:$true, CCOp:$cc),
+def MOVCCr : AI<(ops GPR:$dst, GPR:$false, GPR:$true, ccop:$cc),
                 "mov$cc $dst, $true",
                 [(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc))]>,
                 RegConstraint<"$false = $dst">;
 
-def MOVCCs : AI<(ops GPR:$dst, GPR:$false, so_reg:$true, CCOp:$cc),
+def MOVCCs : AI<(ops GPR:$dst, GPR:$false, so_reg:$true, ccop:$cc),
                 "mov$cc $dst, $true",
                 [(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true,imm:$cc))]>,
                 RegConstraint<"$false = $dst">;
 
-def MOVCCi : AI<(ops GPR:$dst, GPR:$false, so_imm:$true, CCOp:$cc),
+def MOVCCi : AI<(ops GPR:$dst, GPR:$false, so_imm:$true, ccop:$cc),
                 "mov$cc $dst, $true",
                 [(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true,imm:$cc))]>,
                 RegConstraint<"$false = $dst">;

diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td
index 141c1ec45e17e1c2ae5b28813e4911fad5e3a49a..45b6411863efee3f3b65cfec55e45728155a7453 100644 (file)
--- a/lib/Target/ARM/ARMInstrThumb.td
+++ b/lib/Target/ARM/ARMInstrThumb.td
@@ -207,7 +207,7 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
 }
 
 let isBranch = 1, isTerminator = 1, noResults = 1, isBarrier = 1 in
-  def tBcc : TI<(ops brtarget:$dst, CCOp:$cc), "b$cc $dst",
+  def tBcc : TI<(ops brtarget:$dst, ccop:$cc), "b$cc $dst",
                  [(ARMbrcond bb:$dst, imm:$cc)]>;
 
 //===----------------------------------------------------------------------===//
@@ -503,7 +503,7 @@ def tUXTH  : TI<(ops GPR:$dst, GPR:$src),
 // Expanded by the scheduler into a branch sequence.
 let usesCustomDAGSchedInserter = 1 in  // Expanded by the scheduler.
   def tMOVCCr :
-  PseudoInst<(ops GPR:$dst, GPR:$false, GPR:$true, CCOp:$cc),
+  PseudoInst<(ops GPR:$dst, GPR:$false, GPR:$true, ccop:$cc),
               "@ tMOVCCr $cc",
               [(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc))]>;
 

diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td
index 671e1a48c184343ae8613b074e430a48ee7e9c0b..46fb6dfda5b3eac7ed83d09e156d07f1a1548de6 100644 (file)
--- a/lib/Target/ARM/ARMInstrVFP.td
+++ b/lib/Target/ARM/ARMInstrVFP.td
@@ -344,22 +344,22 @@ def FNMSCS : ASI<(ops SPR:$dst, SPR:$dstin, SPR:$a, SPR:$b),
 // FP Conditional moves.
 //
 
-def FCPYDcc  : ADI<(ops DPR:$dst, DPR:$false, DPR:$true, CCOp:$cc),
+def FCPYDcc  : ADI<(ops DPR:$dst, DPR:$false, DPR:$true, ccop:$cc),
                    "fcpyd$cc $dst, $true",
                    [(set DPR:$dst, (ARMcmov DPR:$false, DPR:$true, imm:$cc))]>,
                    RegConstraint<"$false = $dst">;
 
-def FCPYScc  : ASI<(ops SPR:$dst, SPR:$false, SPR:$true, CCOp:$cc),
+def FCPYScc  : ASI<(ops SPR:$dst, SPR:$false, SPR:$true, ccop:$cc),
                    "fcpys$cc $dst, $true",
                    [(set SPR:$dst, (ARMcmov SPR:$false, SPR:$true, imm:$cc))]>,
                    RegConstraint<"$false = $dst">;
 
-def FNEGDcc  : ADI<(ops DPR:$dst, DPR:$false, DPR:$true, CCOp:$cc),
+def FNEGDcc  : ADI<(ops DPR:$dst, DPR:$false, DPR:$true, ccop:$cc),
                    "fnegd$cc $dst, $true",
                    [(set DPR:$dst, (ARMcneg DPR:$false, DPR:$true, imm:$cc))]>,
                    RegConstraint<"$false = $dst">;
 
-def FNEGScc  : ASI<(ops SPR:$dst, SPR:$false, SPR:$true, CCOp:$cc),
+def FNEGScc  : ASI<(ops SPR:$dst, SPR:$false, SPR:$true, ccop:$cc),
                    "fnegs$cc $dst, $true",
                    [(set SPR:$dst, (ARMcneg SPR:$false, SPR:$true, imm:$cc))]>,
                    RegConstraint<"$false = $dst">;