[ARM64] Fix disassembly logic for extended loads/stores with 32-bit registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205893 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp b/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
index 3a1925d255deae1f48c55d6a1bb1764a337e66b4..294962c5f3591f96c0359cf998f145c4c7778348 100644 (file)
--- a/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
+++ b/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
@@ -1368,10 +1368,10 @@ static DecodeStatus DecodeRegOffsetLdStInstruction(llvm::MCInst &Inst,
 
   DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
 
-  if (extendHi == 0x3)
+  if ((extendHi & 0x3) == 0x3)
     DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
   else
-    DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
+    DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
 
   Inst.addOperand(MCOperand::CreateImm(extend));
   return Success;

diff --git a/test/MC/Disassembler/ARM64/memory.txt b/test/MC/Disassembler/ARM64/memory.txt
index 664f2b4db20dfd2d079fd9194ba89f5904b26186..54556a10b8a8c957ceb0ca4bad86d8bb3f50cd0b 100644 (file)
--- a/test/MC/Disassembler/ARM64/memory.txt
+++ b/test/MC/Disassembler/ARM64/memory.txt
@@ -83,6 +83,8 @@
   0x64 0x00 0x00 0x39
   0x85 0x50 0x00 0x39
   0xe2 0x43 0x00 0x79
+  0x00 0xe8 0x20 0x38
+  0x00 0x48 0x20 0x38
 
 # CHECK: str   x4, [x3]
 # CHECK: str   x2, [sp, #32]
@@ -95,6 +97,8 @@
 # CHECK: strb  w4, [x3]
 # CHECK: strb  w5, [x4, #20]
 # CHECK: strh  w2, [sp, #32]
+# CHECK: strb  w0, [x0, x0, sxtx]
+# CHECK: strb  w0, [x0, w0, uxtw]
 
 #-----------------------------------------------------------------------------
 # Unscaled immediate loads and stores
@@ -422,11 +426,11 @@
   0xe1 0x6b 0xa3 0x3c
   0xe1 0x5b 0xa3 0x3c
 
-# CHECK: str   h0, [x0, x0, uxtw]
+# CHECK: str   h0, [x0, w0, uxtw]
 # CHECK: str   d1, [sp, x3]
-# CHECK: str   d1, [sp, x3, uxtw #3]
+# CHECK: str   d1, [sp, w3, uxtw #3]
 # CHECK: str   q1, [sp, x3]
-# CHECK: str   q1, [sp, x3, uxtw #4]
+# CHECK: str   q1, [sp, w3, uxtw #4]
 
 #-----------------------------------------------------------------------------
 # Load/Store exclusive