Renamed MachineScheduler to ScheduleTopDownLive.

Responding to code review.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148290 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/CodeGen/Passes.h b/include/llvm/CodeGen/Passes.h
index 3655faf553afb079130c8d0dbc37a83ab72c68a0..e7bbf850d92ca4ada9ec0ea9526601f880b00ca6 100644 (file)
--- a/include/llvm/CodeGen/Passes.h
+++ b/include/llvm/CodeGen/Passes.h
@@ -85,7 +85,7 @@ namespace llvm {
   extern char &RegisterCoalescerPassID;
 
   /// MachineScheduler pass - This pass schedules machine instructions.
-  extern char &MachineSchedulerPassID;
+  extern char &MachineSchedulerID;
 
   /// SpillPlacement analysis. Suggest optimal placement of spill code between
   /// basic blocks.

diff --git a/include/llvm/InitializePasses.h b/include/llvm/InitializePasses.h
index 8b7f73857b9400a1dd4ef40d43c7ae36e01577da..d972eb99013cf0e38de7321e46763e9d7df1b590 100644 (file)
--- a/include/llvm/InitializePasses.h
+++ b/include/llvm/InitializePasses.h
@@ -156,7 +156,7 @@ void initializeMachineLICMPass(PassRegistry&);
 void initializeMachineLoopInfoPass(PassRegistry&);
 void initializeMachineLoopRangesPass(PassRegistry&);
 void initializeMachineModuleInfoPass(PassRegistry&);
-void initializeMachineSchedulerPassPass(PassRegistry&);
+void initializeMachineSchedulerPass(PassRegistry&);
 void initializeMachineSinkingPass(PassRegistry&);
 void initializeMachineVerifierPassPass(PassRegistry&);
 void initializeMemCpyOptPass(PassRegistry&);

diff --git a/lib/CodeGen/CodeGen.cpp b/lib/CodeGen/CodeGen.cpp
index de716e0dbc7775cd08ee224424abe3bf33e231f5..cbbf7f50580aa92ab789a3302184c39f84af2b0d 100644 (file)
--- a/lib/CodeGen/CodeGen.cpp
+++ b/lib/CodeGen/CodeGen.cpp
@@ -43,7 +43,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
   initializeProcessImplicitDefsPass(Registry);
   initializePEIPass(Registry);
   initializeRegisterCoalescerPass(Registry);
-  initializeMachineSchedulerPassPass(Registry);
+  initializeMachineSchedulerPass(Registry);
   initializeRenderMachineFunctionPass(Registry);
   initializeSlotIndexesPass(Registry);
   initializeStackProtectorPass(Registry);

diff --git a/lib/CodeGen/MachineScheduler.cpp b/lib/CodeGen/MachineScheduler.cpp
index df706cbec6db4507c6c6764e65f80d3ce3dc3c4d..53cb672dc457624a4155edd68b3a28f477ee933a 100644 (file)
--- a/lib/CodeGen/MachineScheduler.cpp
+++ b/lib/CodeGen/MachineScheduler.cpp
@@ -34,15 +34,15 @@ using namespace llvm;
 //===----------------------------------------------------------------------===//
 
 namespace {
-/// MachineSchedulerPass runs after coalescing and before register allocation.
-class MachineSchedulerPass : public MachineFunctionPass {
+/// MachineScheduler runs after coalescing and before register allocation.
+class MachineScheduler : public MachineFunctionPass {
 public:
   MachineFunction *MF;
   const TargetInstrInfo *TII;
   const MachineLoopInfo *MLI;
   const MachineDominatorTree *MDT;
 
-  MachineSchedulerPass();
+  MachineScheduler();
 
   virtual void getAnalysisUsage(AnalysisUsage &AU) const;
 
@@ -56,11 +56,11 @@ public:
 };
 } // namespace
 
-char MachineSchedulerPass::ID = 0;
+char MachineScheduler::ID = 0;
 
-char &llvm::MachineSchedulerPassID = MachineSchedulerPass::ID;
+char &llvm::MachineSchedulerID = MachineScheduler::ID;
 
-INITIALIZE_PASS_BEGIN(MachineSchedulerPass, "misched",
+INITIALIZE_PASS_BEGIN(MachineScheduler, "misched",
                       "Machine Instruction Scheduler", false, false)
 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
@@ -68,15 +68,15 @@ INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
 INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
 INITIALIZE_PASS_DEPENDENCY(StrongPHIElimination)
 INITIALIZE_PASS_DEPENDENCY(RegisterCoalescer)
-INITIALIZE_PASS_END(MachineSchedulerPass, "misched",
+INITIALIZE_PASS_END(MachineScheduler, "misched",
                     "Machine Instruction Scheduler", false, false)
 
-MachineSchedulerPass::MachineSchedulerPass()
+MachineScheduler::MachineScheduler()
 : MachineFunctionPass(ID), MF(0), MLI(0), MDT(0) {
-  initializeMachineSchedulerPassPass(*PassRegistry::getPassRegistry());
+  initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
 }
 
-void MachineSchedulerPass::getAnalysisUsage(AnalysisUsage &AU) const {
+void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
   AU.setPreservesCFG();
   AU.addRequiredID(MachineDominatorsID);
   AU.addRequired<MachineLoopInfo>();
@@ -102,7 +102,7 @@ namespace {
 /// schedulers.
 class MachineSchedRegistry : public MachinePassRegistryNode {
 public:
-  typedef ScheduleDAGInstrs *(*ScheduleDAGCtor)(MachineSchedulerPass *);
+  typedef ScheduleDAGInstrs *(*ScheduleDAGCtor)(MachineScheduler *);
 
   // RegisterPassParser requires a (misnamed) FunctionPassCtor type.
   typedef ScheduleDAGCtor FunctionPassCtor;
@@ -137,7 +137,7 @@ public:
 
 MachinePassRegistry MachineSchedRegistry::Registry;
 
-static ScheduleDAGInstrs *createDefaultMachineSched(MachineSchedulerPass *P);
+static ScheduleDAGInstrs *createDefaultMachineSched(MachineScheduler *P);
 
 /// MachineSchedOpt allows command line selection of the scheduler.
 static cl::opt<MachineSchedRegistry::ScheduleDAGCtor, false,
@@ -147,45 +147,22 @@ MachineSchedOpt("misched",
                 cl::desc("Machine instruction scheduler to use"));
 
 //===----------------------------------------------------------------------===//
-// Machine Instruction Scheduling Implementation
+// Machine Instruction Scheduling Common Implementation
 //===----------------------------------------------------------------------===//
 
 namespace {
 /// MachineScheduler is an implementation of ScheduleDAGInstrs that schedules
 /// machine instructions while updating LiveIntervals.
-class MachineScheduler : public ScheduleDAGInstrs {
-  MachineSchedulerPass *Pass;
+class ScheduleTopDownLive : public ScheduleDAGInstrs {
+protected:
+  MachineScheduler *Pass;
 public:
-  MachineScheduler(MachineSchedulerPass *P):
+  ScheduleTopDownLive(MachineScheduler *P):
     ScheduleDAGInstrs(*P->MF, *P->MLI, *P->MDT, /*IsPostRA=*/false), Pass(P) {}
-
-  /// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
-  /// time to do some work.
-  virtual void Schedule();
 };
 } // namespace
 
-static ScheduleDAGInstrs *createDefaultMachineSched(MachineSchedulerPass *P) {
-  return new MachineScheduler(P);
-}
-static MachineSchedRegistry
-SchedDefaultRegistry("default", "Activate the scheduler pass, "
-                     "but don't reorder instructions",
-                     createDefaultMachineSched);
-
-/// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
-/// time to do some work.
-void MachineScheduler::Schedule() {
-  BuildSchedGraph(&Pass->getAnalysis<AliasAnalysis>());
-
-  DEBUG(dbgs() << "********** MI Scheduling **********\n");
-  DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
-          SUnits[su].dumpAll(this));
-
-  // TODO: Put interesting things here.
-}
-
-bool MachineSchedulerPass::runOnMachineFunction(MachineFunction &mf) {
+bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
   // Initialize the context of the pass.
   MF = &mf;
   MLI = &getAnalysis<MachineLoopInfo>();
@@ -241,10 +218,45 @@ bool MachineSchedulerPass::runOnMachineFunction(MachineFunction &mf) {
   return true;
 }
 
-void MachineSchedulerPass::print(raw_ostream &O, const Module* m) const {
+void MachineScheduler::print(raw_ostream &O, const Module* m) const {
   // unimplemented
 }
 
+//===----------------------------------------------------------------------===//
+// Placeholder for extending the machine instruction scheduler.
+//===----------------------------------------------------------------------===//
+
+namespace {
+class DefaultMachineScheduler : public ScheduleTopDownLive {
+public:
+  DefaultMachineScheduler(MachineScheduler *P):
+    ScheduleTopDownLive(P) {}
+
+  void Schedule();
+};
+} // namespace
+
+static ScheduleDAGInstrs *createDefaultMachineSched(MachineScheduler *P) {
+  return new DefaultMachineScheduler(P);
+}
+static MachineSchedRegistry
+SchedDefaultRegistry("default", "Activate the scheduler pass, "
+                     "but don't reorder instructions",
+                     createDefaultMachineSched);
+
+
+/// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
+/// time to do some work.
+void DefaultMachineScheduler::Schedule() {
+  BuildSchedGraph(&Pass->getAnalysis<AliasAnalysis>());
+
+  DEBUG(dbgs() << "********** MI Scheduling **********\n");
+  DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
+          SUnits[su].dumpAll(this));
+
+  // TODO: Put interesting things here.
+}
+
 //===----------------------------------------------------------------------===//
 // Machine Instruction Shuffler for Correctness Testing
 //===----------------------------------------------------------------------===//
@@ -252,11 +264,11 @@ void MachineSchedulerPass::print(raw_ostream &O, const Module* m) const {
 #ifndef NDEBUG
 namespace {
 /// Reorder instructions as much as possible.
-class InstructionShuffler : public ScheduleDAGInstrs {
-  MachineSchedulerPass *Pass;
+class InstructionShuffler : public ScheduleTopDownLive {
+  MachineScheduler *Pass;
 public:
-  InstructionShuffler(MachineSchedulerPass *P):
-    ScheduleDAGInstrs(*P->MF, *P->MLI, *P->MDT, /*IsPostRA=*/false), Pass(P) {}
+  InstructionShuffler(MachineScheduler *P):
+    ScheduleTopDownLive(P) {}
 
   /// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
   /// time to do some work.
@@ -266,7 +278,7 @@ public:
 };
 } // namespace
 
-static ScheduleDAGInstrs *createInstructionShuffler(MachineSchedulerPass *P) {
+static ScheduleDAGInstrs *createInstructionShuffler(MachineScheduler *P) {
   return new InstructionShuffler(P);
 }
 static MachineSchedRegistry ShufflerRegistry("shuffle",

diff --git a/lib/CodeGen/RegAllocBasic.cpp b/lib/CodeGen/RegAllocBasic.cpp
index dbddf722d169d9a4126289144892f0af95637edd..570a56e2715d91049e4357f79d3e29a299068521 100644 (file)
--- a/lib/CodeGen/RegAllocBasic.cpp
+++ b/lib/CodeGen/RegAllocBasic.cpp
@@ -129,7 +129,7 @@ RABasic::RABasic(): MachineFunctionPass(ID) {
   initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
   initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
   initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
-  initializeMachineSchedulerPassPass(*PassRegistry::getPassRegistry());
+  initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
   initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
   initializeLiveStacksPass(*PassRegistry::getPassRegistry());
   initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());

diff --git a/lib/CodeGen/RegAllocGreedy.cpp b/lib/CodeGen/RegAllocGreedy.cpp
index 16832ceaf3df037133100bb9b658fa2e17eea945..9fd444fbe38c48235b522923c7bb3babb68b193d 100644 (file)
--- a/lib/CodeGen/RegAllocGreedy.cpp
+++ b/lib/CodeGen/RegAllocGreedy.cpp
@@ -316,7 +316,7 @@ RAGreedy::RAGreedy(): MachineFunctionPass(ID) {
   initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
   initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
   initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
-  initializeMachineSchedulerPassPass(*PassRegistry::getPassRegistry());
+  initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
   initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
   initializeLiveStacksPass(*PassRegistry::getPassRegistry());
   initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
@@ -339,7 +339,7 @@ void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
     AU.addRequiredID(StrongPHIEliminationID);
   AU.addRequiredTransitiveID(RegisterCoalescerPassID);
   if (EnableMachineSched)
-    AU.addRequiredID(MachineSchedulerPassID);
+    AU.addRequiredID(MachineSchedulerID);
   AU.addRequired<CalculateSpillWeights>();
   AU.addRequired<LiveStacks>();
   AU.addPreserved<LiveStacks>();