def ST_FD : MSAPat<(store (v2f64 MSA128D:$ws), addrRegImm:$addr),
(ST_D MSA128D:$ws, addrRegImm:$addr)>;
+class MSA_FABS_PSEUDO_DESC_BASE<RegisterClass RCWD, RegisterClass RCWS = RCWD,
+ InstrItinClass itin = NoItinerary> :
+ MipsPseudo<(outs RCWD:$wd),
+ (ins RCWS:$ws),
+ [(set RCWD:$wd, (fabs RCWS:$ws))]> {
+ InstrItinClass Itinerary = itin;
+}
+def FABS_W : MSA_FABS_PSEUDO_DESC_BASE<MSA128W>,
+ PseudoInstExpansion<(FMAX_A_W MSA128W:$wd, MSA128W:$ws,
+ MSA128W:$ws)>;
+def FABS_D : MSA_FABS_PSEUDO_DESC_BASE<MSA128D>,
+ PseudoInstExpansion<(FMAX_A_D MSA128D:$wd, MSA128D:$ws,
+ MSA128D:$ws)>;
+
class MSABitconvertPat<ValueType DstVT, ValueType SrcVT,
RegisterClass DstRC, list<Predicate> preds = [HasMSA]> :
MSAPat<(DstVT (bitconvert SrcVT:$src)),
setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal);
if (Ty != MVT::v8f16) {
+ setOperationAction(ISD::FABS, Ty, Legal);
setOperationAction(ISD::FADD, Ty, Legal);
setOperationAction(ISD::FDIV, Ty, Legal);
setOperationAction(ISD::FLOG2, Ty, Legal);
; CHECK: .size fdiv_v2f64
}
+define void @fabs_v4f32(<4 x float>* %c, <4 x float>* %a) nounwind {
+ ; CHECK: fabs_v4f32:
+
+ %1 = load <4 x float>* %a
+ ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
+ %2 = tail call <4 x float> @llvm.fabs.v4f32 (<4 x float> %1)
+ ; CHECK-DAG: fmax_a.w [[R3:\$w[0-9]+]], [[R1]], [[R1]]
+ store <4 x float> %2, <4 x float>* %c
+ ; CHECK-DAG: st.w [[R3]], 0($4)
+
+ ret void
+ ; CHECK: .size fabs_v4f32
+}
+
+define void @fabs_v2f64(<2 x double>* %c, <2 x double>* %a) nounwind {
+ ; CHECK: fabs_v2f64:
+
+ %1 = load <2 x double>* %a
+ ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
+ %2 = tail call <2 x double> @llvm.fabs.v2f64 (<2 x double> %1)
+ ; CHECK-DAG: fmax_a.d [[R3:\$w[0-9]+]], [[R1]], [[R1]]
+ store <2 x double> %2, <2 x double>* %c
+ ; CHECK-DAG: st.d [[R3]], 0($4)
+
+ ret void
+ ; CHECK: .size fabs_v2f64
+}
+
define void @fsqrt_v4f32(<4 x float>* %c, <4 x float>* %a) nounwind {
; CHECK: fsqrt_v4f32:
; CHECK: .size fsqrt_v2f64
}
+declare <4 x float> @llvm.fabs.v4f32(<4 x float> %Val)
+declare <2 x double> @llvm.fabs.v2f64(<2 x double> %Val)
declare <4 x float> @llvm.sqrt.v4f32(<4 x float> %Val)
declare <2 x double> @llvm.sqrt.v2f64(<2 x double> %Val)