Updates to match change of getRegForInlineAsmConstraint prototype

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26305 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 533499cbc0adf2a37fdf65fdf81cae6e675e6139..79211debc9957731f234b8ec41e8e6e3fe93128a 100644 (file)
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -745,7 +745,8 @@ bool TargetLowering::isOperandValidForConstraint(SDOperand Op,
 
 
 std::vector<unsigned> TargetLowering::
-getRegForInlineAsmConstraint(const std::string &Constraint) const {
+getRegForInlineAsmConstraint(const std::string &Constraint,
+                             MVT::ValueType VT) const {
   // Not a physreg, must not be a register reference or something.
   if (Constraint[0] != '{') return std::vector<unsigned>();
   assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");

diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 568d94f9e84e076306a75cef73e7ebfeb25a5ed9..243c51d7c9d97d8ac543fe17edadb0c1191735b6 100644 (file)
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -999,7 +999,8 @@ PPCTargetLowering::getConstraintType(char ConstraintLetter) const {
 
 
 std::vector<unsigned> PPCTargetLowering::
-getRegForInlineAsmConstraint(const std::string &Constraint) const {
+getRegForInlineAsmConstraint(const std::string &Constraint,
+                             MVT::ValueType VT) const {
   if (Constraint.size() == 1) {
     switch (Constraint[0]) {      // GCC RS6000 Constraint Letters
     default: break;  // Unknown constriant letter
@@ -1051,7 +1052,7 @@ getRegForInlineAsmConstraint(const std::string &Constraint) const {
   }
   
   // Handle explicit register names.
-  return TargetLowering::getRegForInlineAsmConstraint(Constraint);
+  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
 }
 
 // isOperandValidForConstraint

diff --git a/lib/Target/PowerPC/PPCISelLowering.h b/lib/Target/PowerPC/PPCISelLowering.h
index 681d41a85340f511d205c752a06b7fb46b4a328a..a1ce5545c32be22d26cb3f3c284ffc2a1e82212d 100644 (file)
--- a/lib/Target/PowerPC/PPCISelLowering.h
+++ b/lib/Target/PowerPC/PPCISelLowering.h
@@ -99,7 +99,8 @@ namespace llvm {
     
     ConstraintType getConstraintType(char ConstraintLetter) const;
     std::vector<unsigned> 
-      getRegForInlineAsmConstraint(const std::string &Constraint) const;
+      getRegForInlineAsmConstraint(const std::string &Constraint,
+                                   MVT::ValueType VT) const;
     bool isOperandValidForConstraint(SDOperand Op, char ConstraintLetter);
   };
 }

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 7c84850683ed445e7cf100826f11b73b1239c4ac..bbf590b8ac3aaf55cc014989bb265630d849aa65 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -1961,7 +1961,8 @@ void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
 }
 
 std::vector<unsigned> X86TargetLowering::
-getRegForInlineAsmConstraint(const std::string &Constraint) const {
+getRegForInlineAsmConstraint(const std::string &Constraint,
+                             MVT::ValueType VT) const {
   if (Constraint.size() == 1) {
     // FIXME: not handling fp-stack yet!
     // FIXME: not handling MMX registers yet ('y' constraint).
@@ -1993,5 +1994,5 @@ getRegForInlineAsmConstraint(const std::string &Constraint) const {
   }
   
   // Handle explicit register names.
-  return TargetLowering::getRegForInlineAsmConstraint(Constraint);
+  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
 }

diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h
index 93030136475b450dd5334207708ef5ce51dde174..375320c7714d87a9fcedd197c01f9d350d12059c 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.h
+++ b/lib/Target/X86/X86ISelLowering.h
@@ -224,7 +224,8 @@ namespace llvm {
     SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
 
     std::vector<unsigned> 
-      getRegForInlineAsmConstraint(const std::string &Constraint) const;
+      getRegForInlineAsmConstraint(const std::string &Constraint,
+                                   MVT::ValueType VT) const;
   private:
     // C Calling Convention implementation.
     std::vector<SDOperand> LowerCCCArguments(Function &F, SelectionDAG &DAG);