unsigned SrcReg, bool isKill, int FrameIdx,
const TargetRegisterClass *RC) const {
const MachineFunction &MF = *MBB.getParent();
- unsigned Opc = getStoreRegOpcode(RC, RI.needsStackRealignment(MF));
+ bool isAligned = (RI.getStackAlignment() >= 16) ||
+ RI.needsStackRealignment(MF);
+ unsigned Opc = getStoreRegOpcode(RC, isAligned);
addFrameReference(BuildMI(MBB, MI, get(Opc)), FrameIdx)
.addReg(SrcReg, false, false, isKill);
}
SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
- unsigned Opc = getStoreRegOpcode(RC, RI.needsStackRealignment(MF));
+ bool isAligned = (RI.getStackAlignment() >= 16) ||
+ RI.needsStackRealignment(MF);
+ unsigned Opc = getStoreRegOpcode(RC, isAligned);
MachineInstrBuilder MIB = BuildMI(MF, get(Opc));
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
MIB = X86InstrAddOperand(MIB, Addr[i]);
unsigned DestReg, int FrameIdx,
const TargetRegisterClass *RC) const{
const MachineFunction &MF = *MBB.getParent();
- unsigned Opc = getLoadRegOpcode(RC, RI.needsStackRealignment(MF));
+ bool isAligned = (RI.getStackAlignment() >= 16) ||
+ RI.needsStackRealignment(MF);
+ unsigned Opc = getLoadRegOpcode(RC, isAligned);
addFrameReference(BuildMI(MBB, MI, get(Opc), DestReg), FrameIdx);
}
SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
- unsigned Opc = getLoadRegOpcode(RC, RI.needsStackRealignment(MF));
+ bool isAligned = (RI.getStackAlignment() >= 16) ||
+ RI.needsStackRealignment(MF);
+ unsigned Opc = getLoadRegOpcode(RC, isAligned);
MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
MIB = X86InstrAddOperand(MIB, Addr[i]);
const MachineFunction &MF = DAG.getMachineFunction();
if (FoldedLoad) {
MVT VT = *RC->vt_begin();
- Load = DAG.getTargetNode(getLoadRegOpcode(RC, RI.needsStackRealignment(MF)),
+ bool isAligned = (RI.getStackAlignment() >= 16) ||
+ RI.needsStackRealignment(MF);
+ Load = DAG.getTargetNode(getLoadRegOpcode(RC, isAligned),
VT, MVT::Other,
&AddrOps[0], AddrOps.size());
NewNodes.push_back(Load);
AddrOps.pop_back();
AddrOps.push_back(SDOperand(NewNode, 0));
AddrOps.push_back(Chain);
- SDNode *Store =
- DAG.getTargetNode(getStoreRegOpcode(DstRC,
- RI.needsStackRealignment(MF)),
- MVT::Other, &AddrOps[0], AddrOps.size());
+ bool isAligned = (RI.getStackAlignment() >= 16) ||
+ RI.needsStackRealignment(MF);
+ SDNode *Store = DAG.getTargetNode(getStoreRegOpcode(DstRC, isAligned),
+ MVT::Other, &AddrOps[0], AddrOps.size());
NewNodes.push_back(Store);
}