ARM: dts: qcom: apq8064 - add i2c3 node for panel.

This patch adds i2c3 node which is used for panel control on IFC6410.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>

diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
index f97339abbfaa734db08e829f03d1ee43b1a72d1c..a7c939ba88730bf7b1e7076dc9b592e9d2b5577d 100644 (file)
--- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
@@ -87,6 +87,16 @@
                        };
                };
 
+               gsbi3: gsbi@16200000 {
+                       status = "okay";
+                       qcom,mode = <GSBI_PROT_I2C>;
+                       i2c3: i2c@16280000 {
+                               status = "okay";
+                               pinctrl-0 = <&i2c3_pins>;
+                               pinctrl-names = "default";
+                       };
+               };
+
                gsbi@12440000 {
                        status = "okay";
                        qcom,mode = <GSBI_PROT_I2C>;

diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 345ea081c76544b2780b4a4002926f70c982d2ca..df2061ec630d16e71165d78ce71a8a4a32092271 100644 (file)
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -120,6 +120,13 @@
                                        function = "gsbi1";
                                };
                        };
+
+                       i2c3_pins: i2c3 {
+                               mux {
+                                       pins = "gpio8", "gpio9";
+                                       function = "gsbi3";
+                               };
+                       };
                };
 
                intc: interrupt-controller@2000000 {
@@ -233,6 +240,26 @@
                        };
                };
 
+               gsbi3: gsbi@16200000 {
+                       status = "disabled";
+                       compatible = "qcom,gsbi-v1.0.0";
+                       reg = <0x16200000 0x100>;
+                       clocks = <&gcc GSBI3_H_CLK>;
+                       clock-names = "iface";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
+
+                       i2c3: i2c@16280000 {
+                               compatible = "qcom,i2c-qup-v1.1.1";
+                               reg = <0x16280000 0x1000>;
+                               interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
+                               clocks = <&gcc GSBI3_QUP_CLK>,
+                                        <&gcc GSBI3_H_CLK>;
+                               clock-names = "core", "iface";
+                       };
+               };
+
                gsbi7: gsbi@16600000 {
                        status = "disabled";
                        compatible = "qcom,gsbi-v1.0.0";