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Add QPR_8 as a superreg class of SPR_8 and DPR_8.
author
Evan Cheng
<evan.cheng@apple.com>
Tue, 3 Nov 2009 05:50:57 +0000
(
05:50
+0000)
committer
Evan Cheng
<evan.cheng@apple.com>
Tue, 3 Nov 2009 05:50:57 +0000
(
05:50
+0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85869
91177308
-0d34-0410-b5e6-
96231b3b80d8
lib/Target/ARM/ARMRegisterInfo.td
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diff --git
a/lib/Target/ARM/ARMRegisterInfo.td
b/lib/Target/ARM/ARMRegisterInfo.td
index 7d6b0bb9c4a85b53839e8c0242457108b248b973..d393e8d7e3e26e58a8cf93b5eb57fe7c01be976e 100644
(file)
--- a/
lib/Target/ARM/ARMRegisterInfo.td
+++ b/
lib/Target/ARM/ARMRegisterInfo.td
@@
-357,6
+357,13
@@
def QPR_VFP2 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
let SubRegClassList = [SPR, SPR, SPR, SPR, DPR_VFP2, DPR_VFP2];
}
+// Subset of QPR that have DPR_8 and SPR_8 subregs.
+def QPR_8 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
+ 128,
+ [Q0, Q1, Q2, Q3]> {
+ let SubRegClassList = [SPR_8, SPR_8, SPR_8, SPR_8, DPR_8, DPR_8];
+}
+
// Condition code registers.
def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]>;