drm/i915: Force CL2 off in CHV x1 PHY
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Wed, 8 Jul 2015 20:45:58 +0000 (23:45 +0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 26 Aug 2015 12:37:39 +0000 (14:37 +0200)
We can choose to leave the display PHY CL2 powerdown up to some hardware
signals, or we can force it. The BXT code forces the nonexistent CL2 in
the x1 PHY to power down. Follow suit on CHV. Maybe it can still save
some extra power by disabling some extra logic in CL1, or something.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Deepak S <deepak.s@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_runtime_pm.c

index 6ed7141c9505458f3aa48d4d0a43d1ba6a7b12e3..439bb27a63be91370b0bf99093e61f0f021fd0ba 100644 (file)
@@ -1149,6 +1149,7 @@ enum skl_disp_power_wells {
 #define   DPIO_SUS_CLK_CONFIG_GATE_CLKREQ      (3 << 0)
 
 #define CHV_CMN_DW30                   0x8178
+#define   DPIO_CL2_LDOFUSE_PWRENB      (1 << 6)
 #define   DPIO_LRC_BYPASS              (1 << 3)
 
 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
index ef043b2c06b26f9a091f94fd8be37dfb52188182..a0df156ee92efeab9c4a17b1c25107cfe5eebea2 100644 (file)
@@ -996,6 +996,15 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
                tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
                tmp |= DPIO_DYNPWRDOWNEN_CH1;
                vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
+       } else {
+               /*
+                * Force the non-existing CL2 off. BXT does this
+                * too, so maybe it saves some power even though
+                * CL2 doesn't exist?
+                */
+               tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
+               tmp |= DPIO_CL2_LDOFUSE_PWRENB;
+               vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
        }
 
        mutex_unlock(&dev_priv->sb_lock);