The big change here is to handle printing/emission of X86II::MRMSrcMem

instructions.  Right now the only users are load instructions, and Misha's
spill code

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4812 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/Printer.cpp b/lib/Target/X86/Printer.cpp
index 464855508fc4f5fd07169e6d6fd6528195d511be..61ac823ee684331855a2ba0968329593678e92e4 100644 (file)
--- a/lib/Target/X86/Printer.cpp
+++ b/lib/Target/X86/Printer.cpp
@@ -68,6 +68,28 @@ bool Printer::runOnFunction (Function & F)
   return false;
 }
 
+static bool isReg(const MachineOperand &MO) {
+  return MO.getType() == MachineOperand::MO_VirtualRegister ||
+         MO.getType() == MachineOperand::MO_MachineRegister;
+}
+
+static bool isImmediate(const MachineOperand &MO) {
+  return MO.getType() == MachineOperand::MO_SignExtendedImmed ||
+         MO.getType() == MachineOperand::MO_UnextendedImmed;
+}
+
+static bool isScale(const MachineOperand &MO) {
+  return isImmediate(MO) &&
+           (MO.getImmedValue() == 1 || MO.getImmedValue() == 2 ||
+            MO.getImmedValue() == 4 || MO.getImmedValue() == 8);
+}
+
+static bool isMem(const MachineInstr *MI, unsigned Op) {
+  return Op+4 <= MI->getNumOperands() &&
+         isReg(MI->getOperand(Op  )) && isScale(MI->getOperand(Op+1)) &&
+         isReg(MI->getOperand(Op+2)) && isImmediate(MI->getOperand(Op+3));
+}
+
 static void printOp(std::ostream &O, const MachineOperand &MO,
                     const MRegisterInfo &RI) {
   switch (MO.getType()) {
@@ -88,6 +110,36 @@ static void printOp(std::ostream &O, const MachineOperand &MO,
   }
 }
 
+static void printMemReference(std::ostream &O, const MachineInstr *MI,
+                              unsigned Op, const MRegisterInfo &RI) {
+  assert(isMem(MI, Op) && "Invalid memory reference!");
+  const MachineOperand &BaseReg  = MI->getOperand(Op);
+  const MachineOperand &Scale    = MI->getOperand(Op+1);
+  const MachineOperand &IndexReg = MI->getOperand(Op+2);
+  const MachineOperand &Disp     = MI->getOperand(Op+3);
+
+  O << "[";
+  bool NeedPlus = false;
+  if (BaseReg.getReg()) {
+    printOp(O, BaseReg, RI);
+    NeedPlus = true;
+  }
+
+  if (IndexReg.getReg()) {
+    if (NeedPlus) O << " + ";
+    if (IndexReg.getImmedValue() != 1)
+      O << IndexReg.getImmedValue() << "*";
+    printOp(O, IndexReg, RI);
+    NeedPlus = true;
+  }
+
+  if (Disp.getImmedValue()) {
+    if (NeedPlus) O << " + ";
+    printOp(O, Disp, RI);
+  }
+  O << "]";
+}
+
 static inline void toHexDigit(std::ostream &O, unsigned char V) {
   if (V >= 10)
     O << (char)('A'+V-10);
@@ -110,15 +162,10 @@ static std::ostream &emitConstant(std::ostream &O, unsigned Val, unsigned Size){
   return O;
 }
 
-
-static bool isReg(const MachineOperand &MO) {
-  return MO.getType() == MachineOperand::MO_VirtualRegister ||
-         MO.getType() == MachineOperand::MO_MachineRegister;
-}
-
-static bool isImmediate(const MachineOperand &MO) {
-  return MO.getType() == MachineOperand::MO_SignExtendedImmed ||
-         MO.getType() == MachineOperand::MO_UnextendedImmed;
+namespace N86 {  // Native X86 Register numbers...
+  enum {
+    EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
+  };
 }
 
 
@@ -127,14 +174,14 @@ static bool isImmediate(const MachineOperand &MO) {
 //
 static unsigned getX86RegNum(unsigned RegNo) {
   switch(RegNo) {
-  case X86::EAX: case X86::AX: case X86::AL: return 0;
-  case X86::ECX: case X86::CX: case X86::CL: return 1;
-  case X86::EDX: case X86::DX: case X86::DL: return 2;
-  case X86::EBX: case X86::BX: case X86::BL: return 3;
-  case X86::ESP: case X86::SP: case X86::AH: return 4;
-  case X86::EBP: case X86::BP: case X86::CH: return 5;
-  case X86::ESI: case X86::SI: case X86::DH: return 6;
-  case X86::EDI: case X86::DI: case X86::BH: return 7;
+  case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
+  case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
+  case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
+  case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
+  case X86::ESP: case X86::SP: case X86::AH: return N86::ESP;
+  case X86::EBP: case X86::BP: case X86::CH: return N86::EBP;
+  case X86::ESI: case X86::SI: case X86::DH: return N86::ESI;
+  case X86::EDI: case X86::DI: case X86::BH: return N86::EDI;
   default:
     assert(RegNo >= MRegisterInfo::FirstVirtualRegister &&
            "Unknown physical register!");
@@ -150,8 +197,94 @@ inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
   return RM | (RegOpcode << 3) | (Mod << 6);
 }
 
-static unsigned char regModRMByte(unsigned ModRMReg, unsigned RegOpcodeField) {
-  return ModRMByte(3, RegOpcodeField, getX86RegNum(ModRMReg));
+static void emitRegModRMByte(std::ostream &O, unsigned ModRMReg,
+                             unsigned RegOpcodeField) {
+  toHex(O, ModRMByte(3, RegOpcodeField, getX86RegNum(ModRMReg)));
+}
+
+inline static void emitSIBByte(std::ostream &O, unsigned SS, unsigned Index,
+                               unsigned Base) {
+  // SIB byte is in the same format as the ModRMByte...
+  toHex(O, ModRMByte(SS, Index, Base));
+}
+
+static bool isDisp8(int Value) {
+  return Value == (signed char)Value;
+}
+
+static void emitMemModRMByte(std::ostream &O, const MachineInstr *MI,
+                             unsigned Op, unsigned RegOpcodeField) {
+  assert(isMem(MI, Op) && "Invalid memory reference!");
+  const MachineOperand &BaseReg  = MI->getOperand(Op);
+  const MachineOperand &Scale    = MI->getOperand(Op+1);
+  const MachineOperand &IndexReg = MI->getOperand(Op+2);
+  const MachineOperand &Disp     = MI->getOperand(Op+3);
+
+  // Is a SIB byte needed?
+  if (IndexReg.getReg() == 0 && BaseReg.getReg() != X86::ESP) {
+    if (BaseReg.getReg() == 0) {  // Just a displacement?
+      // Emit special case [disp32] encoding
+      toHex(O, ModRMByte(0, RegOpcodeField, 5));
+      emitConstant(O, Disp.getImmedValue(), 4);
+    } else {
+      unsigned BaseRegNo = getX86RegNum(BaseReg.getReg());
+      if (Disp.getImmedValue() == 0 && BaseRegNo != N86::EBP) {
+        // Emit simple indirect register encoding... [EAX] f.e.
+        toHex(O, ModRMByte(0, RegOpcodeField, BaseRegNo));
+      } else if (isDisp8(Disp.getImmedValue())) {
+        // Emit the disp8 encoding... [REG+disp8]
+        toHex(O, ModRMByte(1, RegOpcodeField, BaseRegNo));
+        emitConstant(O, Disp.getImmedValue(), 1);
+      } else {
+        // Emit the most general non-SIB encoding: [REG+disp32]
+        toHex(O, ModRMByte(1, RegOpcodeField, BaseRegNo));
+        emitConstant(O, Disp.getImmedValue(), 4);
+      }
+    }
+
+  } else {  // We need a SIB byte, so start by outputting the ModR/M byte first
+    assert(IndexReg.getReg() != X86::ESP && "Cannot use ESP as index reg!");
+
+    bool ForceDisp32 = false;
+    if (BaseReg.getReg() == 0) {
+      // If there is no base register, we emit the special case SIB byte with
+      // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
+      toHex(O, ModRMByte(0, RegOpcodeField, 4));
+      ForceDisp32 = true;
+    } else if (Disp.getImmedValue() == 0) {
+      // Emit no displacement ModR/M byte
+      toHex(O, ModRMByte(0, RegOpcodeField, 4));
+    } else if (isDisp8(Disp.getImmedValue())) {
+      // Emit the disp8 encoding...
+      toHex(O, ModRMByte(1, RegOpcodeField, 4));
+    } else {
+      // Emit the normal disp32 encoding...
+      toHex(O, ModRMByte(2, RegOpcodeField, 4));
+    }
+
+    // Calculate what the SS field value should be...
+    static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
+    unsigned SS = SSTable[Scale.getImmedValue()];
+
+    if (BaseReg.getReg() == 0) {
+      // Handle the SIB byte for the case where there is no base.  The
+      // displacement has already been output.
+      assert(IndexReg.getReg() && "Index register must be specified!");
+      emitSIBByte(O, SS, getX86RegNum(IndexReg.getReg()), 5);
+    } else {
+      unsigned BaseRegNo = getX86RegNum(BaseReg.getReg());
+      unsigned IndexRegNo = getX86RegNum(IndexReg.getReg());
+      emitSIBByte(O, SS, IndexRegNo, BaseRegNo);
+    }
+
+    // Do we need to output a displacement?
+    if (Disp.getImmedValue() != 0 || ForceDisp32) {
+      if (!ForceDisp32 && isDisp8(Disp.getImmedValue()))
+        emitConstant(O, Disp.getImmedValue(), 1);
+      else
+        emitConstant(O, Disp.getImmedValue(), 4);
+    }
+  }
 }
 
 
@@ -236,7 +369,7 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
     toHex(O, getBaseOpcodeFor(Opcode)) << " ";
     unsigned ModRMReg = MI->getOperand(0).getReg();
     unsigned ExtraReg = MI->getOperand(MI->getNumOperands()-1).getReg();
-    toHex(O, regModRMByte(ModRMReg, getX86RegNum(ExtraReg)));
+    emitRegModRMByte(O, ModRMReg, getX86RegNum(ExtraReg));
 
     O << "\n\t\t\t\t";
     O << getName(MI->getOpCode()) << " ";
@@ -268,7 +401,7 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
     toHex(O, getBaseOpcodeFor(Opcode)) << " ";
     unsigned ModRMReg = MI->getOperand(MI->getNumOperands()-1).getReg();
     unsigned ExtraReg = MI->getOperand(0).getReg();
-    toHex(O, regModRMByte(ModRMReg, getX86RegNum(ExtraReg)));
+    emitRegModRMByte(O, ModRMReg, getX86RegNum(ExtraReg));
 
     O << "\n\t\t\t\t";
     O << getName(MI->getOpCode()) << " ";
@@ -279,6 +412,35 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
     return;
   }
 
+  case X86II::MRMSrcMem: {
+    // These instructions are the same as MRMSrcReg, but instead of having a
+    // register reference for the mod/rm field, it's a memory reference.
+
+    //I(MOVmr8      , "movb",  0x8A,             0, X86II::MRMSrcMem) 
+    // R8  = [mem]  8A/r
+
+    assert(isReg(MI->getOperand(0)) &&
+           (MI->getNumOperands() == 1+4 && isMem(MI, 1)) || 
+           (MI->getNumOperands() == 2+4 && isReg(MI->getOperand(1)) && 
+            isMem(MI, 2))
+           && "Bad format for MRMDestReg!");
+    if (MI->getNumOperands() == 2+4 &&
+        MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
+      O << "**";
+
+    toHex(O, getBaseOpcodeFor(Opcode)) << " ";
+    unsigned ExtraReg = MI->getOperand(0).getReg();
+    emitMemModRMByte(O, MI, MI->getNumOperands()-4, getX86RegNum(ExtraReg));
+
+    O << "\n\t\t\t\t";
+    O << getName(MI->getOpCode()) << " ";
+    printOp(O, MI->getOperand(0), RI);
+    O << ", <SIZE> PTR ";
+    printMemReference(O, MI, MI->getNumOperands()-4, RI);
+    O << "\n";
+    return;
+  }
+
   case X86II::MRMS0r: case X86II::MRMS1r:
   case X86II::MRMS2r: case X86II::MRMS3r:
   case X86II::MRMS4r: case X86II::MRMS5r:
@@ -302,7 +464,7 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
       O << "**";
 
     toHex(O, getBaseOpcodeFor(Opcode)) << " ";
-    toHex(O, regModRMByte(MI->getOperand(0).getReg(), ExtraField));
+    emitRegModRMByte(O, MI->getOperand(0).getReg(), ExtraField);
 
     if (MI->getNumOperands() == 3) {
       unsigned Size = 4;
@@ -322,7 +484,6 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
   }
 
   case X86II::MRMDestMem:
-  case X86II::MRMSrcMem:
   default:
     O << "\t\t\t-"; MI->print(O, TM); break;
   }

diff --git a/lib/Target/X86/X86AsmPrinter.cpp b/lib/Target/X86/X86AsmPrinter.cpp
index 464855508fc4f5fd07169e6d6fd6528195d511be..61ac823ee684331855a2ba0968329593678e92e4 100644 (file)
--- a/lib/Target/X86/X86AsmPrinter.cpp
+++ b/lib/Target/X86/X86AsmPrinter.cpp
@@ -68,6 +68,28 @@ bool Printer::runOnFunction (Function & F)
   return false;
 }
 
+static bool isReg(const MachineOperand &MO) {
+  return MO.getType() == MachineOperand::MO_VirtualRegister ||
+         MO.getType() == MachineOperand::MO_MachineRegister;
+}
+
+static bool isImmediate(const MachineOperand &MO) {
+  return MO.getType() == MachineOperand::MO_SignExtendedImmed ||
+         MO.getType() == MachineOperand::MO_UnextendedImmed;
+}
+
+static bool isScale(const MachineOperand &MO) {
+  return isImmediate(MO) &&
+           (MO.getImmedValue() == 1 || MO.getImmedValue() == 2 ||
+            MO.getImmedValue() == 4 || MO.getImmedValue() == 8);
+}
+
+static bool isMem(const MachineInstr *MI, unsigned Op) {
+  return Op+4 <= MI->getNumOperands() &&
+         isReg(MI->getOperand(Op  )) && isScale(MI->getOperand(Op+1)) &&
+         isReg(MI->getOperand(Op+2)) && isImmediate(MI->getOperand(Op+3));
+}
+
 static void printOp(std::ostream &O, const MachineOperand &MO,
                     const MRegisterInfo &RI) {
   switch (MO.getType()) {
@@ -88,6 +110,36 @@ static void printOp(std::ostream &O, const MachineOperand &MO,
   }
 }
 
+static void printMemReference(std::ostream &O, const MachineInstr *MI,
+                              unsigned Op, const MRegisterInfo &RI) {
+  assert(isMem(MI, Op) && "Invalid memory reference!");
+  const MachineOperand &BaseReg  = MI->getOperand(Op);
+  const MachineOperand &Scale    = MI->getOperand(Op+1);
+  const MachineOperand &IndexReg = MI->getOperand(Op+2);
+  const MachineOperand &Disp     = MI->getOperand(Op+3);
+
+  O << "[";
+  bool NeedPlus = false;
+  if (BaseReg.getReg()) {
+    printOp(O, BaseReg, RI);
+    NeedPlus = true;
+  }
+
+  if (IndexReg.getReg()) {
+    if (NeedPlus) O << " + ";
+    if (IndexReg.getImmedValue() != 1)
+      O << IndexReg.getImmedValue() << "*";
+    printOp(O, IndexReg, RI);
+    NeedPlus = true;
+  }
+
+  if (Disp.getImmedValue()) {
+    if (NeedPlus) O << " + ";
+    printOp(O, Disp, RI);
+  }
+  O << "]";
+}
+
 static inline void toHexDigit(std::ostream &O, unsigned char V) {
   if (V >= 10)
     O << (char)('A'+V-10);
@@ -110,15 +162,10 @@ static std::ostream &emitConstant(std::ostream &O, unsigned Val, unsigned Size){
   return O;
 }
 
-
-static bool isReg(const MachineOperand &MO) {
-  return MO.getType() == MachineOperand::MO_VirtualRegister ||
-         MO.getType() == MachineOperand::MO_MachineRegister;
-}
-
-static bool isImmediate(const MachineOperand &MO) {
-  return MO.getType() == MachineOperand::MO_SignExtendedImmed ||
-         MO.getType() == MachineOperand::MO_UnextendedImmed;
+namespace N86 {  // Native X86 Register numbers...
+  enum {
+    EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
+  };
 }
 
 
@@ -127,14 +174,14 @@ static bool isImmediate(const MachineOperand &MO) {
 //
 static unsigned getX86RegNum(unsigned RegNo) {
   switch(RegNo) {
-  case X86::EAX: case X86::AX: case X86::AL: return 0;
-  case X86::ECX: case X86::CX: case X86::CL: return 1;
-  case X86::EDX: case X86::DX: case X86::DL: return 2;
-  case X86::EBX: case X86::BX: case X86::BL: return 3;
-  case X86::ESP: case X86::SP: case X86::AH: return 4;
-  case X86::EBP: case X86::BP: case X86::CH: return 5;
-  case X86::ESI: case X86::SI: case X86::DH: return 6;
-  case X86::EDI: case X86::DI: case X86::BH: return 7;
+  case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
+  case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
+  case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
+  case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
+  case X86::ESP: case X86::SP: case X86::AH: return N86::ESP;
+  case X86::EBP: case X86::BP: case X86::CH: return N86::EBP;
+  case X86::ESI: case X86::SI: case X86::DH: return N86::ESI;
+  case X86::EDI: case X86::DI: case X86::BH: return N86::EDI;
   default:
     assert(RegNo >= MRegisterInfo::FirstVirtualRegister &&
            "Unknown physical register!");
@@ -150,8 +197,94 @@ inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
   return RM | (RegOpcode << 3) | (Mod << 6);
 }
 
-static unsigned char regModRMByte(unsigned ModRMReg, unsigned RegOpcodeField) {
-  return ModRMByte(3, RegOpcodeField, getX86RegNum(ModRMReg));
+static void emitRegModRMByte(std::ostream &O, unsigned ModRMReg,
+                             unsigned RegOpcodeField) {
+  toHex(O, ModRMByte(3, RegOpcodeField, getX86RegNum(ModRMReg)));
+}
+
+inline static void emitSIBByte(std::ostream &O, unsigned SS, unsigned Index,
+                               unsigned Base) {
+  // SIB byte is in the same format as the ModRMByte...
+  toHex(O, ModRMByte(SS, Index, Base));
+}
+
+static bool isDisp8(int Value) {
+  return Value == (signed char)Value;
+}
+
+static void emitMemModRMByte(std::ostream &O, const MachineInstr *MI,
+                             unsigned Op, unsigned RegOpcodeField) {
+  assert(isMem(MI, Op) && "Invalid memory reference!");
+  const MachineOperand &BaseReg  = MI->getOperand(Op);
+  const MachineOperand &Scale    = MI->getOperand(Op+1);
+  const MachineOperand &IndexReg = MI->getOperand(Op+2);
+  const MachineOperand &Disp     = MI->getOperand(Op+3);
+
+  // Is a SIB byte needed?
+  if (IndexReg.getReg() == 0 && BaseReg.getReg() != X86::ESP) {
+    if (BaseReg.getReg() == 0) {  // Just a displacement?
+      // Emit special case [disp32] encoding
+      toHex(O, ModRMByte(0, RegOpcodeField, 5));
+      emitConstant(O, Disp.getImmedValue(), 4);
+    } else {
+      unsigned BaseRegNo = getX86RegNum(BaseReg.getReg());
+      if (Disp.getImmedValue() == 0 && BaseRegNo != N86::EBP) {
+        // Emit simple indirect register encoding... [EAX] f.e.
+        toHex(O, ModRMByte(0, RegOpcodeField, BaseRegNo));
+      } else if (isDisp8(Disp.getImmedValue())) {
+        // Emit the disp8 encoding... [REG+disp8]
+        toHex(O, ModRMByte(1, RegOpcodeField, BaseRegNo));
+        emitConstant(O, Disp.getImmedValue(), 1);
+      } else {
+        // Emit the most general non-SIB encoding: [REG+disp32]
+        toHex(O, ModRMByte(1, RegOpcodeField, BaseRegNo));
+        emitConstant(O, Disp.getImmedValue(), 4);
+      }
+    }
+
+  } else {  // We need a SIB byte, so start by outputting the ModR/M byte first
+    assert(IndexReg.getReg() != X86::ESP && "Cannot use ESP as index reg!");
+
+    bool ForceDisp32 = false;
+    if (BaseReg.getReg() == 0) {
+      // If there is no base register, we emit the special case SIB byte with
+      // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
+      toHex(O, ModRMByte(0, RegOpcodeField, 4));
+      ForceDisp32 = true;
+    } else if (Disp.getImmedValue() == 0) {
+      // Emit no displacement ModR/M byte
+      toHex(O, ModRMByte(0, RegOpcodeField, 4));
+    } else if (isDisp8(Disp.getImmedValue())) {
+      // Emit the disp8 encoding...
+      toHex(O, ModRMByte(1, RegOpcodeField, 4));
+    } else {
+      // Emit the normal disp32 encoding...
+      toHex(O, ModRMByte(2, RegOpcodeField, 4));
+    }
+
+    // Calculate what the SS field value should be...
+    static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
+    unsigned SS = SSTable[Scale.getImmedValue()];
+
+    if (BaseReg.getReg() == 0) {
+      // Handle the SIB byte for the case where there is no base.  The
+      // displacement has already been output.
+      assert(IndexReg.getReg() && "Index register must be specified!");
+      emitSIBByte(O, SS, getX86RegNum(IndexReg.getReg()), 5);
+    } else {
+      unsigned BaseRegNo = getX86RegNum(BaseReg.getReg());
+      unsigned IndexRegNo = getX86RegNum(IndexReg.getReg());
+      emitSIBByte(O, SS, IndexRegNo, BaseRegNo);
+    }
+
+    // Do we need to output a displacement?
+    if (Disp.getImmedValue() != 0 || ForceDisp32) {
+      if (!ForceDisp32 && isDisp8(Disp.getImmedValue()))
+        emitConstant(O, Disp.getImmedValue(), 1);
+      else
+        emitConstant(O, Disp.getImmedValue(), 4);
+    }
+  }
 }
 
 
@@ -236,7 +369,7 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
     toHex(O, getBaseOpcodeFor(Opcode)) << " ";
     unsigned ModRMReg = MI->getOperand(0).getReg();
     unsigned ExtraReg = MI->getOperand(MI->getNumOperands()-1).getReg();
-    toHex(O, regModRMByte(ModRMReg, getX86RegNum(ExtraReg)));
+    emitRegModRMByte(O, ModRMReg, getX86RegNum(ExtraReg));
 
     O << "\n\t\t\t\t";
     O << getName(MI->getOpCode()) << " ";
@@ -268,7 +401,7 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
     toHex(O, getBaseOpcodeFor(Opcode)) << " ";
     unsigned ModRMReg = MI->getOperand(MI->getNumOperands()-1).getReg();
     unsigned ExtraReg = MI->getOperand(0).getReg();
-    toHex(O, regModRMByte(ModRMReg, getX86RegNum(ExtraReg)));
+    emitRegModRMByte(O, ModRMReg, getX86RegNum(ExtraReg));
 
     O << "\n\t\t\t\t";
     O << getName(MI->getOpCode()) << " ";
@@ -279,6 +412,35 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
     return;
   }
 
+  case X86II::MRMSrcMem: {
+    // These instructions are the same as MRMSrcReg, but instead of having a
+    // register reference for the mod/rm field, it's a memory reference.
+
+    //I(MOVmr8      , "movb",  0x8A,             0, X86II::MRMSrcMem) 
+    // R8  = [mem]  8A/r
+
+    assert(isReg(MI->getOperand(0)) &&
+           (MI->getNumOperands() == 1+4 && isMem(MI, 1)) || 
+           (MI->getNumOperands() == 2+4 && isReg(MI->getOperand(1)) && 
+            isMem(MI, 2))
+           && "Bad format for MRMDestReg!");
+    if (MI->getNumOperands() == 2+4 &&
+        MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
+      O << "**";
+
+    toHex(O, getBaseOpcodeFor(Opcode)) << " ";
+    unsigned ExtraReg = MI->getOperand(0).getReg();
+    emitMemModRMByte(O, MI, MI->getNumOperands()-4, getX86RegNum(ExtraReg));
+
+    O << "\n\t\t\t\t";
+    O << getName(MI->getOpCode()) << " ";
+    printOp(O, MI->getOperand(0), RI);
+    O << ", <SIZE> PTR ";
+    printMemReference(O, MI, MI->getNumOperands()-4, RI);
+    O << "\n";
+    return;
+  }
+
   case X86II::MRMS0r: case X86II::MRMS1r:
   case X86II::MRMS2r: case X86II::MRMS3r:
   case X86II::MRMS4r: case X86II::MRMS5r:
@@ -302,7 +464,7 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
       O << "**";
 
     toHex(O, getBaseOpcodeFor(Opcode)) << " ";
-    toHex(O, regModRMByte(MI->getOperand(0).getReg(), ExtraField));
+    emitRegModRMByte(O, MI->getOperand(0).getReg(), ExtraField);
 
     if (MI->getNumOperands() == 3) {
       unsigned Size = 4;
@@ -322,7 +484,6 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
   }
 
   case X86II::MRMDestMem:
-  case X86II::MRMSrcMem:
   default:
     O << "\t\t\t-"; MI->print(O, TM); break;
   }