GPU: Rogue_M: update to 1.31_2 version & support gpu pd.
authorzxl <zhuangxl@rock-chips.com>
Mon, 18 Jan 2016 09:38:21 +0000 (17:38 +0800)
committerzxl <zhuangxl@rock-chips.com>
Mon, 18 Jan 2016 11:04:28 +0000 (19:04 +0800)
1. Add GPU pd support.
2. Disable RD power island.

Change-Id: Ib2ee45c647d0bed5aaa5c4f0c591c0f527f3d11e
Signed-off-by: zxl <zhuangxl@rock-chips.com>
drivers/gpu/rogue_m/include/pvrversion.h
drivers/gpu/rogue_m/system/rk3368/rk_init.c
drivers/gpu/rogue_m/system/rk3368/rk_init.h
drivers/gpu/rogue_m/system/rk3368/sysconfig.c

index 9349d5551a9b5917a237eb408649cd2b8a4a064f..62e3f33c3995b62947eec39132eb60d15d4b5b60 100644 (file)
@@ -49,27 +49,33 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *  Rogue KM Version Note
  *
  *  L 1.17:
- *          Support gpu disable dvfs case.
- *          Add rk_tf_check_version to compatible for rk3328.
+ *             Support gpu disable dvfs case.
+ *             Add rk_tf_check_version to compatible for rk3328.
  *  L 1.18:
- *                     If fix freq,then don't force to drop freq to the lowest.
+ *             If fix freq,then don't force to drop freq to the lowest.
  *
  *  M 1.21:
- *          Merge 1.5_RTM3604260 DDK code.
+ *             Merge 1.5_RTM3604260 DDK code.
  *  M 1.24:
- *          Merge 1.5_ED3653583 DDK code.
+ *             Merge 1.5_ED3653583 DDK code.
  *  M 1.28:
- *         Merge 1.5_ED3776568 DDK code.
+ *             Merge 1.5_ED3776568 DDK code.
  *  M 1.29
- *         1. Reopen bEnableRDPowIsland since it doesn't appear splash screen when click the drawerbutton.
- *         2. Don't set PVR_ANDROID_HAS_SET_BUFFERS_DATASPACE by default.
- *         3. Remove hGPUUtilLock to avoid dead lock.
- *         4. Get raw ion_device by IonDevAcquire.
+ *             1. Reopen bEnableRDPowIsland since it doesn't appear splash screen when click the drawerbutton.
+ *             2. Don't set PVR_ANDROID_HAS_SET_BUFFERS_DATASPACE by default.
+ *             3. Remove hGPUUtilLock to avoid dead lock.
+ *             4. Get raw ion_device by IonDevAcquire.
  *  M 1.31
- *         1. Merge 1.5_ED3830101 DDK code.
+ *             1. Merge 1.5_ED3830101 DDK code.
  *  M 1.31+
- *          1. Let Rogue M support kernel 4.4.
- *          2. Close OPEN_GPU_PD temporarily.
+ *             1. Let Rogue M support kernel 4.4.
+ *             2. Close OPEN_GPU_PD temporarily.
+ *  M 1.31_2
+ *             1. Add GPU dvfs support.
+ *             2. Adjust the code indentation.
+ *             3. Use late_initcall instead of module_init to load gpu driver.
+ *             4. Add GPU pd support.
+ *             5. Disable RD power island.
  */
 
 #define PVR_STR(X) #X
index 644c3e17e233864df1e8563bb1dfce5485b232ff..205fc569d0ea2fa78efb110fdd3e0f98e2df06b7 100644 (file)
@@ -24,6 +24,7 @@
 #include <linux/clk-private.h>
 #else
 #include <linux/clk-provider.h>
+#include <linux/pm_runtime.h>
 #endif
 #include <linux/pm_opp.h>
 #include <asm/compiler.h>
@@ -1802,6 +1803,7 @@ static IMG_VOID RgxDisableClock(IMG_VOID)
 }
 
 #if OPEN_GPU_PD
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0))
 /*
  * The power management
  * software must power down pd_gpu_1 before power down pd_gpu_0,
@@ -1812,7 +1814,6 @@ static IMG_VOID RgxEnablePower(IMG_VOID)
        struct rk_context *platform;
 
        platform = dev_get_drvdata(&gpsPVRLDMDev->dev);
-
        PVR_ASSERT(platform != NULL);
 
        if (!platform->bEnablePd && platform->pd_gpu_0 && platform->pd_gpu_1) {
@@ -1829,7 +1830,6 @@ static IMG_VOID RgxDisablePower(IMG_VOID)
        struct rk_context *platform;
 
        platform = dev_get_drvdata(&gpsPVRLDMDev->dev);
-
        PVR_ASSERT(platform != NULL);
 
        if (platform->bEnablePd && platform->pd_gpu_0 && platform->pd_gpu_1) {
@@ -1840,7 +1840,39 @@ static IMG_VOID RgxDisablePower(IMG_VOID)
                PVR_DPF((PVR_DBG_WARNING, "Failed to enable gpu_pd clock!"));
        }
 }
+#else
+static IMG_VOID RgxEnablePower(IMG_VOID)
+{
+       struct rk_context *platform;
+
+       platform = dev_get_drvdata(&gpsPVRLDMDev->dev);
+       PVR_ASSERT(platform != NULL);
+
+       if (!platform->bEnablePd) {
+               pm_runtime_get_sync(&gpsPVRLDMDev->dev);
+               platform->bEnablePd = IMG_TRUE;
+       } else {
+               PVR_DPF((PVR_DBG_WARNING, "Failed to enable gpu_pd clock!"));
+       }
+}
+
+static IMG_VOID RgxDisablePower(IMG_VOID)
+{
+       struct rk_context *platform;
+
+       platform = dev_get_drvdata(&gpsPVRLDMDev->dev);
+
+       PVR_ASSERT(platform != NULL);
+
+       if (platform->bEnablePd) {
+               pm_runtime_put(&gpsPVRLDMDev->dev);
+               platform->bEnablePd = IMG_FALSE;
+       } else {
+               PVR_DPF((PVR_DBG_WARNING, "Failed to enable gpu_pd clock!"));
+       }
+}
 #endif
+#endif //end of OPEN_GPU_PD
 
 IMG_VOID RgxResume(IMG_VOID)
 {
@@ -1905,6 +1937,7 @@ IMG_VOID RgxRkInit(IMG_VOID)
        spin_lock_init(&platform->timer_lock);
 
 #if OPEN_GPU_PD
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0))
        platform->pd_gpu_0 = devm_clk_get(&gpsPVRLDMDev->dev, "pd_gpu_0");
        if (IS_ERR_OR_NULL(platform->pd_gpu_0)) {
                PVR_DPF((PVR_DBG_ERROR,
@@ -1918,7 +1951,10 @@ IMG_VOID RgxRkInit(IMG_VOID)
                         "RgxRkInit: Failed to find pd_gpu_1 clock source"));
                goto fail1;
        }
+#else
+       pm_runtime_enable(&gpsPVRLDMDev->dev);
 #endif
+#endif //end of OPEN_GPU_PD
 
        platform->aclk_gpu_mem =
            devm_clk_get(&gpsPVRLDMDev->dev, "aclk_gpu_mem");
@@ -1980,11 +2016,10 @@ fail4:
 fail3:
        platform->aclk_gpu_mem = NULL;
 fail2:
-#if OPEN_GPU_PD
+#if OPEN_GPU_PD && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0))
        platform->pd_gpu_1 = NULL;
 fail1:
        platform->pd_gpu_0 = NULL;
-fail0:
 #else
         return;
 #endif //end of OPEN_GPU_PD
@@ -2010,13 +2045,17 @@ IMG_VOID RgxRkUnInit(IMG_VOID)
                platform->aclk_gpu_mem = NULL;
        }
 #if OPEN_GPU_PD
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0))
        if (platform->pd_gpu_1) {
                platform->pd_gpu_1 = NULL;
        }
        if (platform->pd_gpu_0) {
                platform->pd_gpu_0 = NULL;
        }
+#else
+       pm_runtime_disable(&gpsPVRLDMDev->dev);
 #endif
+#endif //OPEN_GPU_PD
 
        if (platform->dvfs_enabled) {
 #if RK33_DVFS_SUPPORT
index 8cb126312994be52231435a585d787fe23621835..bd4d0491e65b434659efd77f51e3a7534f4f1760 100644 (file)
@@ -17,7 +17,7 @@
 #define RK33_USE_CUSTOMER_GET_GPU_UTIL      0
 
 #define RK33_USE_CL_COUNT_UTILS             0
-#define OPEN_GPU_PD                         0
+#define OPEN_GPU_PD                         1
 
 //USE_KTHREAD and USE_HRTIMER are mutually exclusive
 #define USE_KTHREAD                         0
index 30a77c78ffcb6e5cc64b6bc6451161f6882c5152..016c30e86c2db7a046aef387591f68d790451890 100644 (file)
@@ -159,7 +159,7 @@ PVRSRV_ERROR SysCreateConfigData(PVRSRV_SYSTEM_CONFIG **ppsSysConfig, void *hDev
         */
        gsRGXTimingInfo.ui32CoreClockSpeed        = RGX_RK_CORE_CLOCK_SPEED;
        gsRGXTimingInfo.bEnableActivePM           = IMG_TRUE;
-       gsRGXTimingInfo.bEnableRDPowIsland        = IMG_TRUE;
+       gsRGXTimingInfo.bEnableRDPowIsland        = IMG_FALSE;
        gsRGXTimingInfo.ui32ActivePMLatencyms     = SYS_RGX_ACTIVE_POWER_LATENCY_MS;
 
        /*