/// Return with a flag operand, matched by 'blr'
RET_FLAG,
};
- }
+ }
+
+ /// Define some predicates that are used for node matching.
+ namespace PPC {
+ /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
+ /// specifies a splat of a single element that is suitable for input to
+ /// VSPLTB/VSPLTH/VSPLTW.
+ bool isSplatShuffleMask(SDNode *N) { return false; } // FIXME:
+
+ /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
+ /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
+ unsigned getVSPLTImmediate(SDNode *N) { return 0; } // FIXME:
+ }
class PPCTargetLowering : public TargetLowering {
int VarArgsFrameIndex; // FrameIndex for start of varargs area.
return ((unsigned)N->getValue() & 0xFFFF0000U) == (unsigned)N->getValue();
}], HI16>;
+// VSPLT_get_imm xform function: convert vector_shuffle mask to VSPLT* imm.
+def VSPLT_get_imm : SDNodeXForm<build_vector, [{
+ return getI32Imm(PPC::getVSPLTImmediate(N));
+}]>;
+
+def VSPLT_shuffle_mask : PatLeaf<(build_vector), [{
+ return PPC::isSplatShuffleMask(N);
+}], VSPLT_get_imm>;
//===----------------------------------------------------------------------===//
// PowerPC Flag Definitions.
[]>, isPPC64;
}
+
let PPC970_Unit = 5 in { // VALU Operations.
// VA-Form instructions. 3-input AltiVec ops.
def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
def VSPLTH : VXForm_1<588, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
"vsplth $vD, $vB, $UIMM", VecPerm,
[]>;
-def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
- "vspltw $vD, $vB, $UIMM", VecPerm,
- []>;
+
+//def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
+// "vspltw $vD, $vB, $UIMM", VecPerm,
+// [(set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB), (undef),
+// VSPLT_shuffle_mask:$UIMM))]>;
// VX-Form Pseudo Instructions
[]>;
}
+
//===----------------------------------------------------------------------===//
// DWARF Pseudo Instructions
//