Expand 64bit {SHL,SHR,SRA}_PARTS on sparcv9.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201718 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp
index 7ad87b34af66020588a677ca25eabf036223b0ac..32c278b6689f4dc477feeb31eb4d5275e1a37501 100644 (file)
--- a/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/lib/Target/Sparc/SparcISelLowering.cpp
@@ -1556,6 +1556,10 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
 
     setOperationAction(ISD::UMULO,     MVT::i64, Custom);
     setOperationAction(ISD::SMULO,     MVT::i64, Custom);
+
+    setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
+    setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
+    setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
   }
 
   // VASTART needs to be custom lowered to use the VarArgsFrameIndex.

diff --git a/test/CodeGen/SPARC/parts.ll b/test/CodeGen/SPARC/parts.ll
new file mode 100644 (file)
index 0000000..57add49
--- /dev/null
+++ b/test/CodeGen/SPARC/parts.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=sparcv9    | FileCheck %s
+  
+; CHECK-LABEL: test
+; CHECK:        srl %i1, 0, %o2
+; CHECK-NEXT:   or %g0, %i2, %o0
+; CHECK-NEXT:   call __ashlti3
+; CHECK-NEXT:   or %g0, %i3, %o1
+; CHECK-NEXT:   or %g0, %o0, %i0
+  
+define i128 @test(i128 %a, i128 %b) {
+entry:
+    %tmp = shl i128 %b, %a
+    ret i128 %tmp
+}