Fix the encoding of mrrc and mcrr family of instructions. Also add testcases for...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123837 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 5161f88df2b6f74e9125241bc5e756ad563c8e93..8018fe748af31ed5db8cf99462d6e71aba9a7f40 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -3745,28 +3745,28 @@ def MRC2 : ABXI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
   let Inst{19-16} = CRn;
 }
 
-def MCRR : ABI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc,
+def MCRR : ABI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
                GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
-               NoItinerary, "mcrr", "\t$cop, $opc, $Rt, $Rt2, $CRm",
+               NoItinerary, "mcrr", "\t$cop, $opc1, $Rt, $Rt2, $CRm",
                [/* For disassembly only; pattern left blank */]> {
   let Inst{23-20} = 0b0100;
   
   bits<4> Rt;
   bits<4> Rt2;
   bits<4> cop;
-  bits<3> opc1;
+  bits<4> opc1;
   bits<4> CRm;
   
   let Inst{15-12} = Rt;
   let Inst{19-16} = Rt2;
   let Inst{11-8}  = cop;
-  let Inst{7-5}   = opc1;
+  let Inst{7-4}   = opc1;
   let Inst{3-0}   = CRm;
 }
 
-def MCRR2 : ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc,
+def MCRR2 : ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
                  GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
-                 NoItinerary, "mcrr2\t$cop, $opc, $Rt, $Rt2, $CRm",
+                 NoItinerary, "mcrr2\t$cop, $opc1, $Rt, $Rt2, $CRm",
                  [/* For disassembly only; pattern left blank */]> {
   let Inst{31-28} = 0b1111;
   let Inst{23-20} = 0b0100;
@@ -3774,38 +3774,38 @@ def MCRR2 : ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc,
   bits<4> Rt;
   bits<4> Rt2;
   bits<4> cop;
-  bits<3> opc1;
+  bits<4> opc1;
   bits<4> CRm;
   
   let Inst{15-12} = Rt;
   let Inst{19-16} = Rt2;
   let Inst{11-8}  = cop;
-  let Inst{7-5}   = opc1;
+  let Inst{7-4}   = opc1;
   let Inst{3-0}   = CRm;
 }
 
-def MRRC : ABI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc,
+def MRRC : ABI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
                GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
-               NoItinerary, "mrrc", "\t$cop, $opc, $Rt, $Rt2, $CRm",
+               NoItinerary, "mrrc", "\t$cop, $opc1, $Rt, $Rt2, $CRm",
                [/* For disassembly only; pattern left blank */]> {
   let Inst{23-20} = 0b0101;
   
   bits<4> Rt;
   bits<4> Rt2;
   bits<4> cop;
-  bits<3> opc1;
+  bits<4> opc1;
   bits<4> CRm;
   
   let Inst{15-12} = Rt;
   let Inst{19-16} = Rt2;
   let Inst{11-8}  = cop;
-  let Inst{7-5}   = opc1;
+  let Inst{7-4}   = opc1;
   let Inst{3-0}   = CRm;
 }
 
-def MRRC2 : ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc,
+def MRRC2 : ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
                  GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
-                 NoItinerary, "mrrc2\t$cop, $opc, $Rt, $Rt2, $CRm",
+                 NoItinerary, "mrrc2\t$cop, $opc1, $Rt, $Rt2, $CRm",
                  [/* For disassembly only; pattern left blank */]> {
   let Inst{31-28} = 0b1111;
   let Inst{23-20} = 0b0101;
@@ -3813,13 +3813,13 @@ def MRRC2 : ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc,
   bits<4> Rt;
   bits<4> Rt2;
   bits<4> cop;
-  bits<3> opc1;
+  bits<4> opc1;
   bits<4> CRm;
   
   let Inst{15-12} = Rt;
   let Inst{19-16} = Rt2;
   let Inst{11-8}  = cop;
-  let Inst{7-5}   = opc1;
+  let Inst{7-4}   = opc1;
   let Inst{3-0}   = CRm;
 }
 

diff --git a/test/MC/ARM/arm_instructions.s b/test/MC/ARM/arm_instructions.s
index 588e8e5e16fd33d05c2c9ddccd81e84fb445fae1..4b250b3163e54725a4477cc1baf8c2fe0ba76bb7 100644 (file)
--- a/test/MC/ARM/arm_instructions.s
+++ b/test/MC/ARM/arm_instructions.s
@@ -135,3 +135,22 @@
         isb
 @ CHECK: mrs  r8, cpsr @ encoding: [0x00,0x80,0x0f,0xe1]
         mrs  r8, cpsr
+
+@ CHECK: mcr  p7, #1, r5, c1, c1, #4 @ encoding: [0x91,0x57,0x21,0xee]
+        mcr  p7, #1, r5, c1, c1, #4
+@ CHECK: mrc  p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xee]
+        mrc  p14, #0, r1, c1, c2, #4
+@ CHECK: mcrr  p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x44,0xec]
+        mcrr  p7, #1, r5, r4, c1
+@ CHECK: mrrc  p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x54,0xec]
+        mrrc  p7, #1, r5, r4, c1
+
+@ CHECK: mcr2  p7, #1, r5, c1, c1, #4 @ encoding: [0x91,0x57,0x21,0xfe]
+        mcr2  p7, #1, r5, c1, c1, #4
+@ CHECK: mrc2  p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xfe]
+        mrc2  p14, #0, r1, c1, c2, #4
+@ CHECK: mcrr2  p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x44,0xfc]
+        mcrr2  p7, #1, r5, r4, c1
+@ CHECK: mrrc2  p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x54,0xfc]
+        mrrc2  p7, #1, r5, r4, c1
+