Thumb assembly parsing and encoding for ADD(register) instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137759 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index fce361ab03f2707624e86bf7e5c3ba2a370d862b..3fdc7c90c3adc93f210d58e2016896ef7d33f979 100644 (file)
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -2757,6 +2757,15 @@ bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
       static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
       static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
     return true;
+
+  // Register-register 'add' for thumb does not have a cc_out operand
+  // when there are only two register operands.
+  if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
+      static_cast<ARMOperand*>(Operands[3])->isReg() &&
+      static_cast<ARMOperand*>(Operands[4])->isReg() &&
+      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
+    return true;
+
   return false;
 }
 

diff --git a/test/MC/ARM/basic-thumb-instructions.s b/test/MC/ARM/basic-thumb-instructions.s
new file mode 100644 (file)
index 0000000..9c2bee7
--- /dev/null
+++ b/test/MC/ARM/basic-thumb-instructions.s
@@ -0,0 +1,21 @@
+@ RUN: llvm-mc -triple=thumbv6-apple-darwin -show-encoding < %s | FileCheck %s
+  .syntax unified
+  .globl _func
+
+@ Check that the assembler can handle the documented syntax from the ARM ARM.
+@ For complex constructs like shifter operands, check more thoroughly for them
+@ once then spot check that following instructions accept the form generally.
+@ This gives us good coverage while keeping the overall size of the test
+@ more reasonable.
+
+_func:
+@ CHECK: _func
+
+@------------------------------------------------------------------------------
+@ ADD (register)
+@------------------------------------------------------------------------------
+        adds r1, r2, r3
+        add r2, r8
+
+@ CHECK: adds  r1, r2, r3              @ encoding: [0xd1,0x18]
+@ CHECK: add   r2, r8                  @ encoding: [0x42,0x44]