Eliminate CMPri, which is a synonym for SUBCCri

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24805 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td
index 04fb7fe4f5988301f65a55b39d8d55e550ffed1c..0971695edc45d17c0106bc2fd23ab6eb45ebcb44 100644 (file)
--- a/lib/Target/Sparc/SparcInstrInfo.td
+++ b/lib/Target/Sparc/SparcInstrInfo.td
@@ -94,13 +94,6 @@ let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
     def RETL: F3_2<2, 0b111000, (ops),
                    "retl", [(ret)]>;
 }
-// CMP is a special case of SUBCC where destination is ignored, by setting it to
-// %g0 (hardwired zero).
-// FIXME: should keep track of the fact that it defs the integer condition codes
-let rd = 0 in
-  def CMPri: F3_2<2, 0b010100,
-                  (ops IntRegs:$b, i32imm:$c),
-                  "cmp $b, $c", []>;
 
 // Section B.1 - Load Integer Instructions, p. 90
 def LDSBrr : F3_1<3, 0b001001,
@@ -520,6 +513,8 @@ def FABSS : F3_3<2, 0b110100, 0b000001001,
                  (ops FPRegs:$dst, FPRegs:$src),
                  "fabss $src, $dst",
                  [(set FPRegs:$dst, (fabs FPRegs:$src))]>;
+// FIXME: ADD FNEGD/FABSD pseudo instructions.
+
 
 // Floating-point Square Root Instructions, p.145
 def FSQRTS : F3_3<2, 0b110100, 0b000101001, 

diff --git a/lib/Target/Sparc/SparcV8ISelSimple.cpp b/lib/Target/Sparc/SparcV8ISelSimple.cpp
index 2e3530c3cf2590aec32e4147f46ec8222e2893bb..c7d364d2fc73cbb46a7af1bff1db33e92ea743a9 100644 (file)
--- a/lib/Target/Sparc/SparcV8ISelSimple.cpp
+++ b/lib/Target/Sparc/SparcV8ISelSimple.cpp
@@ -1062,7 +1062,7 @@ void V8ISel::visitBranchInst(BranchInst &I) {
       // CondReg=(<condition>);
       // If (CondReg==0) goto notTakenSuccMBB;
       unsigned CondReg = getReg (I.getCondition ());
-      BuildMI (BB, V8::CMPri, 2).addSImm (0).addReg (CondReg);
+      BuildMI (BB, V8::SUBCCri, 2, V8::G0).addReg(CondReg).addSImm(0);
       BuildMI (BB, V8::BE, 1).addMBB (notTakenSuccMBB);
       BuildMI (BB, V8::BA, 1).addMBB (takenSuccMBB);
       return;

diff --git a/lib/Target/SparcV8/SparcV8ISelSimple.cpp b/lib/Target/SparcV8/SparcV8ISelSimple.cpp
index 2e3530c3cf2590aec32e4147f46ec8222e2893bb..c7d364d2fc73cbb46a7af1bff1db33e92ea743a9 100644 (file)
--- a/lib/Target/SparcV8/SparcV8ISelSimple.cpp
+++ b/lib/Target/SparcV8/SparcV8ISelSimple.cpp
@@ -1062,7 +1062,7 @@ void V8ISel::visitBranchInst(BranchInst &I) {
       // CondReg=(<condition>);
       // If (CondReg==0) goto notTakenSuccMBB;
       unsigned CondReg = getReg (I.getCondition ());
-      BuildMI (BB, V8::CMPri, 2).addSImm (0).addReg (CondReg);
+      BuildMI (BB, V8::SUBCCri, 2, V8::G0).addReg(CondReg).addSImm(0);
       BuildMI (BB, V8::BE, 1).addMBB (notTakenSuccMBB);
       BuildMI (BB, V8::BA, 1).addMBB (takenSuccMBB);
       return;

diff --git a/lib/Target/SparcV8/SparcV8InstrInfo.td b/lib/Target/SparcV8/SparcV8InstrInfo.td
index 04fb7fe4f5988301f65a55b39d8d55e550ffed1c..0971695edc45d17c0106bc2fd23ab6eb45ebcb44 100644 (file)
--- a/lib/Target/SparcV8/SparcV8InstrInfo.td
+++ b/lib/Target/SparcV8/SparcV8InstrInfo.td
@@ -94,13 +94,6 @@ let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
     def RETL: F3_2<2, 0b111000, (ops),
                    "retl", [(ret)]>;
 }
-// CMP is a special case of SUBCC where destination is ignored, by setting it to
-// %g0 (hardwired zero).
-// FIXME: should keep track of the fact that it defs the integer condition codes
-let rd = 0 in
-  def CMPri: F3_2<2, 0b010100,
-                  (ops IntRegs:$b, i32imm:$c),
-                  "cmp $b, $c", []>;
 
 // Section B.1 - Load Integer Instructions, p. 90
 def LDSBrr : F3_1<3, 0b001001,
@@ -520,6 +513,8 @@ def FABSS : F3_3<2, 0b110100, 0b000001001,
                  (ops FPRegs:$dst, FPRegs:$src),
                  "fabss $src, $dst",
                  [(set FPRegs:$dst, (fabs FPRegs:$src))]>;
+// FIXME: ADD FNEGD/FABSD pseudo instructions.
+
 
 // Floating-point Square Root Instructions, p.145
 def FSQRTS : F3_3<2, 0b110100, 0b000101001,