ARM: mvebu: update Armada XP DT for dynamic frequency scaling

In order to support dynamic frequency scaling:

 * the cpuclk Device Tree node needs to be updated to describe a
   second set of registers describing the PMU DFS registers.

 * the clock-latency property of the CPUs must be filled, otherwise
   the ondemand and conservative cpufreq governors refuse to work. The
   latency is high because the cost of a frequency transition is quite
   high on those CPUs.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1404920715-19834-5-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index 1257ff1ed278e68a33793eb9cf0c40be08e0b169..2592e1c13560039c0a1396b63026934b12bb305c 100644 (file)
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -34,6 +34,7 @@
                        compatible = "marvell,sheeva-v7";
                        reg = <0>;
                        clocks = <&cpuclk 0>;
+                       clock-latency = <1000000>;
                };
 
                cpu@1 {
@@ -41,6 +42,7 @@
                        compatible = "marvell,sheeva-v7";
                        reg = <1>;
                        clocks = <&cpuclk 1>;
+                       clock-latency = <1000000>;
                };
        };
 

diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 3396b25b39e179cb1a444435adfa28c87385e8ed..480e237a870fa42c86dca6ab7dd5585d6345956a 100644 (file)
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -36,6 +36,7 @@
                        compatible = "marvell,sheeva-v7";
                        reg = <0>;
                        clocks = <&cpuclk 0>;
+                       clock-latency = <1000000>;
                };
 
                cpu@1 {
@@ -43,6 +44,7 @@
                        compatible = "marvell,sheeva-v7";
                        reg = <1>;
                        clocks = <&cpuclk 1>;
+                       clock-latency = <1000000>;
                };
        };
 

diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index 6da84bf40aaf48849d308453755c1eca3605396b..2c7b1fef470350714a9f9c5df7b25f42708019de 100644 (file)
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -37,6 +37,7 @@
                        compatible = "marvell,sheeva-v7";
                        reg = <0>;
                        clocks = <&cpuclk 0>;
+                       clock-latency = <1000000>;
                };
 
                cpu@1 {
@@ -44,6 +45,7 @@
                        compatible = "marvell,sheeva-v7";
                        reg = <1>;
                        clocks = <&cpuclk 1>;
+                       clock-latency = <1000000>;
                };
 
                cpu@2 {
@@ -51,6 +53,7 @@
                        compatible = "marvell,sheeva-v7";
                        reg = <2>;
                        clocks = <&cpuclk 2>;
+                       clock-latency = <1000000>;
                };
 
                cpu@3 {
@@ -58,6 +61,7 @@
                        compatible = "marvell,sheeva-v7";
                        reg = <3>;
                        clocks = <&cpuclk 3>;
+                       clock-latency = <1000000>;
                };
        };
 

diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 5902e8359c9165c33cc265b0a304df33acb640b5..bff9f6c18db1358dd7d70aa9b9de0e40c054da20 100644 (file)
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -99,7 +99,7 @@
                        cpuclk: clock-complex@18700 {
                                #clock-cells = <1>;
                                compatible = "marvell,armada-xp-cpu-clock";
-                               reg = <0x18700 0xA0>;
+                               reg = <0x18700 0xA0>, <0x1c054 0x10>;
                                clocks = <&coreclk 1>;
                        };