return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
}
}
+ // fold (xor (and x, y), y) -> (and (not x), y)
+ if (N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
+ N0->getOperand(1) == N1) {
+ SDValue X = N0->getOperand(0);
+ SDValue NotX = DAG.getNode(ISD::XOR, X.getDebugLoc(), VT, X,
+ DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
+ AddToWorkList(NotX.getNode());
+ return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NotX, N1);
+ }
// fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
if (N1C && N0.getOpcode() == ISD::XOR) {
ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
}
; CHECK:sccwne:
; CHECK: cmp.w r14, r15
-; CHECK: mov.w r2, r15
-; CHECK: rra.w r15
-; CHECK: and.w #1, r15
-; CHECK: xor.w #1, r15
+; CHECK: mov.w r2, r12
+; CHECK: rra.w r12
+; CHECK: mov.w #1, r15
+; CHECK: bic.w r12, r15
define i16 @sccweq(i16 %a, i16 %b) nounwind {
%t1 = icmp eq i16 %a, %b
}
; CHECK:sccwugt:
; CHECK: cmp.w r15, r14
-; CHECK: mov.w r2, r15
-; CHECK: and.w #1, r15
-; CHECK: xor.w #1, r15
+; CHECK: mov.w #1, r15
+; CHECK: bic.w r2, r15
define i16 @sccwuge(i16 %a, i16 %b) nounwind {
%t1 = icmp uge i16 %a, %b
}
; CHECK:sccwult:
; CHECK: cmp.w r14, r15
-; CHECK: mov.w r2, r15
-; CHECK: and.w #1, r15
-; CHECK: xor.w #1, r15
+; CHECK: mov.w #1, r15
+; CHECK: bic.w r2, r15
define i16 @sccwule(i16 %a, i16 %b) nounwind {
%t1 = icmp ule i16 %a, %b
; X32: test8:
; X32: notl %eax
}
+
+define i32 @test9(i32 %a) nounwind {
+ %1 = and i32 %a, 4096
+ %2 = xor i32 %1, 4096
+ ret i32 %2
+; X64: test9:
+; X64: notl [[REG:%[a-z]+]]
+; X64: andl {{.*}}[[REG:%[a-z]+]]
+; X32: test9:
+; X32: notl [[REG:%[a-z]+]]
+; X32: andl {{.*}}[[REG:%[a-z]+]]
+}